/external/llvm/lib/Target/ARM/ |
Thumb2InstrInfo.cpp | 61 unsigned PredReg = 0; 62 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); 109 unsigned PredReg = 0; 110 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; 215 ARMCC::CondCodes Pred, unsigned PredReg, 220 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 237 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 244 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 253 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 259 .addImm((unsigned)Pred).addReg(PredReg).addReg(0 [all...] |
MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); 298 MIB.addImm(Pred).addReg(PredReg); 310 MIB.addImm(Pred).addReg(PredReg);
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Thumb2ITBlockPass.cpp | 171 unsigned PredReg = 0; 172 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
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ARMBaseRegisterInfo.cpp | 403 unsigned PredReg, unsigned MIFlags) const { 414 .addImm(0).addImm(Pred).addReg(PredReg) 760 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 768 Offset, Pred, PredReg, TII); 772 Offset, Pred, PredReg, TII);
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ARMExpandPseudoInsts.cpp | [all...] |
Thumb2SizeReduction.cpp | 581 unsigned PredReg = 0; 582 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { 685 unsigned PredReg = 0; 686 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 782 unsigned PredReg = 0; 783 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); [all...] |
ARMFrameLowering.cpp | 120 unsigned PredReg = 0) { 123 Pred, PredReg, TII, MIFlags); 126 Pred, PredReg, TII, MIFlags); 134 unsigned PredReg = 0) { 136 MIFlags, Pred, PredReg); [all...] |
ARMConstantIslandPass.cpp | [all...] |
ARMISelDAGToDAG.cpp | [all...] |
ARMLoadStoreOptimizer.cpp | 103 ARMCC::CondCodes Pred, unsigned PredReg); 106 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, 120 unsigned PredReg, 126 ARMCC::CondCodes Pred, unsigned PredReg, 336 ARMCC::CondCodes Pred, unsigned PredReg) { 388 .addImm(Pred).addReg(PredReg); 406 .addImm(Pred).addReg(PredReg); 417 unsigned PredReg, unsigned Scratch, DebugLoc dl, 481 .addImm(Pred).addReg(PredReg); 485 .addImm(Pred).addReg(PredReg); [all...] |
ARMBaseInstrInfo.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonHardwareLoops.cpp | 500 unsigned PredReg = Cond[Cond.size()-1].getReg(); 501 MachineInstr *CondI = MRI->getVRegDef(PredReg); [all...] |