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    Searched defs:RegUnits (Results 1 - 4 of 4) sorted by null

  /external/llvm/lib/CodeGen/
InterferenceCache.h 87 /// more than 4 RegUnits.
88 SmallVector<RegUnitInfo, 4> RegUnits;
  /external/llvm/include/llvm/MC/
MCRegisterInfo.h 118 // RegUnits - Points to the list of register units. The low 4 bits holds the
120 uint32_t RegUnits;
161 unsigned NumRegUnits; // Number of regunits.
495 assert(Reg && "Null register has no regunits");
496 // Decode the RegUnits MCRegisterDesc field.
497 unsigned RU = MCRI->get(Reg).RegUnits;
  /external/llvm/utils/TableGen/
RegisterInfoEmitter.cpp 175 std::vector<unsigned> RegUnits;
176 RC.buildRegUnitSet(RegUnits);
178 << ", " << RegBank.getRegUnitSetWeight(RegUnits);
238 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
239 OS << " " << RegUnits.Weight << ", \t// " << i << ": "
240 << RegUnits.Name << "\n";
837 assert(!Roots.empty() && "All regunits must have a root register.");
    [all...]
CodeGenRegisters.h 190 const RegUnitList &getRegUnits() const { return RegUnits; }
194 return makeArrayRef(RegUnits).slice(0, NumNativeRegUnits);
198 // Return true if the RegUnits changed.
203 void adoptRegUnit(unsigned RUID) { RegUnits.push_back(RUID); }
238 RegUnitList RegUnits;
366 void buildRegUnitSet(std::vector<unsigned> &RegUnits) const;
468 SmallVector<RegUnit, 8> RegUnits;
579 RegUnits.resize(RegUnits.size() + 1);
580 RegUnits.back().Roots[0] = R0
    [all...]

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