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    Searched defs:Registers (Results 1 - 12 of 12) sorted by null

  /external/chromium_org/third_party/mesa/src/src/mesa/swrast/
s_atifragshader.c 36 GLfloat Registers[6][4]; /** six temporary registers */
236 COPY_4V(machine->PrevPassRegisters[i], machine->Registers[i]);
265 COPY_4V(machine->Registers[idx],
270 COPY_4V(machine->Registers[idx], machine->PrevPassRegisters[pass_tex]);
272 apply_swizzle(machine->Registers[idx], swizzle);
296 fetch_texel(ctx, tex_coords, 0.0F, idx, machine->Registers[idx]);
346 /* setup the source registers for color and alpha ops */
353 machine->Registers[index - GL_REG_0_ATI]);
536 /* write out the destination registers */
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  /external/chromium_org/v8/src/mips64/
constants-mips64.h 88 // Registers and FPURegisters.
90 // Number of general purpose registers.
94 // Number of registers with HI, LO, and pc.
100 // Number coprocessor registers.
104 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented.
144 class Registers {
200 // the simulator will run through them and print the registers.
559 SELEQZ_C = ((2 << 3) + 4), // COP1 on FPR registers.
560 SELNEZ_C = ((2 << 3) + 7), // COP1 on FPR registers.
717 // registers and other constants
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  /external/mesa3d/src/mesa/swrast/
s_atifragshader.c 36 GLfloat Registers[6][4]; /** six temporary registers */
236 COPY_4V(machine->PrevPassRegisters[i], machine->Registers[i]);
265 COPY_4V(machine->Registers[idx],
270 COPY_4V(machine->Registers[idx], machine->PrevPassRegisters[pass_tex]);
272 apply_swizzle(machine->Registers[idx], swizzle);
296 fetch_texel(ctx, tex_coords, 0.0F, idx, machine->Registers[idx]);
346 /* setup the source registers for color and alpha ops */
353 machine->Registers[index - GL_REG_0_ATI]);
536 /* write out the destination registers */
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  /external/chromium_org/v8/src/mips/
constants-mips.h 126 // Registers and FPURegisters.
128 // Number of general purpose registers.
132 // Number of registers with HI, LO, and pc.
138 // Number coprocessor registers.
142 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented.
182 class Registers {
238 // the simulator will run through them and print the registers.
546 SELEQZ_C = ((2 << 3) + 4), // COP1 on FPR registers.
547 SELNEZ_C = ((2 << 3) + 7), // COP1 on FPR registers.
703 // registers and other constants
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  /external/llvm/utils/TableGen/
RegisterInfoEmitter.cpp 38 // runEnums - Print out enum values for all of the registers.
68 // runEnums - Print out enum values for all of the registers.
71 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
74 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
76 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
93 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
94 OS << " " << Registers[i]->getName() << " = " <<
95 Registers[i]->EnumValue << ",\n";
96 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &
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AsmWriterEmitter.cpp 525 const std::vector<CodeGenRegister*> &Registers) {
527 SmallVector<std::string, 4> AsmNames(Registers.size());
528 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
529 const CodeGenRegister &Reg = *Registers[i];
568 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
580 const std::vector<CodeGenRegister*> &Registers =
594 O << " assert(RegNo && RegNo < " << (Registers.size()+1)
600 emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers);
602 emitRegisterNameString(O, "", Registers);
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CodeGenRegisters.h 47 // Are all super-registers containing this SubRegIndex covered by their
48 // sub-registers?
129 // Lazily compute a map of all sub-registers.
130 // This includes unique entries for all sub-sub-registers.
133 // Compute extra sub-registers by combining the existing sub-registers.
136 // Add this as a super-register to all sub-registers after the sub-register
141 assert(SubRegsComplete && "Must precompute sub-registers");
145 // Add sub-registers to OSet following a pre-order defined by the .td file.
157 // Get the list of super-registers in topological order, small to large
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AsmMatcherEmitter.cpp 196 /// For register classes: the records for all the registers in this class.
197 RegisterSet Registers;
219 // Registers classes are only related to registers classes, and only if
227 std::set_intersection(Registers.begin(), Registers.end(),
228 RHS.Registers.begin(), RHS.Registers.end(),
784 // Collect singleton registers, if used.
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CodeGenRegisters.cpp 130 // Also compute leading super-registers. Each register has a list of
131 // covered-by-subregs super-registers where it appears as the first explicit
139 // registers, so build a symmetric graph by adding links in both ends.
153 // Iterate over all register units in a set of registers.
236 // Map explicit sub-registers first, so the names take precedence.
237 // The inherited sub-registers are mapped below.
341 // sub-registers. By doing this before computeSecondarySubRegs(), we ensure
362 // sub-registers, the other registers won't contribute any more units.
365 // Explicit sub-registers are usually disjoint, so this is a good way o
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  /external/chromium_org/v8/src/arm/
constants-arm.h 33 // Number of registers in normal ARM mode.
659 class Registers {
  /external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 142 // Map of register aliases registers via the .req directive.
404 SmallVector<unsigned, 8> Registers;
447 // A vector register list is a sequential list of 1 to 4 registers.
557 Registers = o.Registers;
649 return Registers;
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  /external/robolectric/lib/main/
sqlite-jdbc-3.7.2.jar 

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