| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 601 /// Regs - This list holds the registers assigned to the values.
605 SmallVector<unsigned, 4> Regs;
609 RegsForValue(const SmallVector<unsigned, 4> ®s,
611 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
622 Regs.push_back(Reg + i);
632 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
689 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT)
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 226 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
227 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
228 if (I == Regs.end())
|
| RegisterInfoEmitter.cpp | 57 const std::vector<CodeGenRegister*> &Regs, bool isCtor);
59 const std::vector<CodeGenRegister*> &Regs,
74 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
171 const CodeGenRegister::Set &Regs = RC.getMembers();
172 if (Regs.empty())
177 OS << " {" << (*Regs.begin())->getWeight(RegBank)
315 const std::vector<CodeGenRegister*> &Regs,
323 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
324 Record *Reg = Regs[i]->TheDef;
342 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace")
[all...] |
| CodeGenRegisters.cpp | 159 RegUnitIterator(const CodeGenRegister::Set &Regs):
160 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() {
349 // SR is composed of multiple sub-regs. Find their names in this register.
[all...] |
| /external/llvm/lib/CodeGen/ |
| ExecutionDepsFix.cpp | 644 SmallVector<LiveReg, 4> Regs;
655 for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end();
659 Regs.insert(i, LR);
663 Regs.push_back(LR);
669 while (!Regs.empty()) {
671 dv = Regs.pop_back_val().Value;
678 DomainValue *Latest = Regs.pop_back_val().Value;
|
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 811 SmallVector<std::pair<unsigned,bool>, 4> Regs;
[all...] |
| ARMLoadStoreOptimizer.cpp | 108 ArrayRef<std::pair<unsigned, bool> > Regs,
410 /// registers in Regs as the register operands that would be loaded / stored.
418 ArrayRef<std::pair<unsigned, bool> > Regs,
421 unsigned NumRegs = Regs.size();
452 NewBase = Regs[NumRegs-1].first;
510 if (Base == Regs[I].first) {
542 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
543 | getKillRegState(Regs[i].second));
638 SmallVector<std::pair<unsigned, bool>, 8> Regs;
646 Regs.push_back(std::make_pair(Reg, isKill))
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 435 SmallVector<SDValue, 4> Regs;
436 Regs.push_back(Val);
440 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
446 Regs.push_back(DAG.getUNDEF(VT));
448 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 895 SmallPtrSet<const SCEV *, 16> &Regs,
908 SmallPtrSet<const SCEV *, 16> &Regs,
912 SmallPtrSet<const SCEV *, 16> &Regs,
[all...] |
