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    Searched defs:SchedModel (Results 1 - 12 of 12) sorted by null

  /external/llvm/lib/MC/
MCSubtargetInfo.cpp 102 assert(Found->Value && "Missing processor SchedModel value");
108 const MCSchedModel *SchedModel = getSchedModelForCPU(CPU);
109 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
  /external/llvm/include/llvm/CodeGen/
TargetSchedule.h 35 MCSchedModel SchedModel;
67 const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
82 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
85 unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
93 return SchedModel.getNumProcResourceKinds();
98 return SchedModel.getProcResource(PIdx);
105 return SchedModel.getProcResource(PIdx)->Name;
140 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; }
145 return SchedModel.getProcResource(PIdx)->BufferSize;
MachineTraceMetrics.h 73 TargetSchedModel SchedModel;
111 /// This is an array with SchedModel.getNumProcResourceKinds() entries.
114 /// These numbers have already been scaled by SchedModel.getResourceFactor().
364 // where Kinds = SchedModel.getNumProcResourceKinds().
373 unsigned Factor = SchedModel.getLatencyFactor();
ScheduleDAGInstrs.h 86 TargetSchedModel SchedModel;
171 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
175 if (!SU->SchedClass && SchedModel.hasInstrSchedModel())
176 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
MachineScheduler.h 548 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
564 const TargetSchedModel *SchedModel;
634 DAG(nullptr), SchedModel(nullptr), Rem(nullptr), Available(ID, Name+".A"),
683 return RetiredMOps * SchedModel->getMicroOpFactor();
691 return std::max(CurrCycle * SchedModel->getLatencyFactor(),
822 const TargetSchedModel *SchedModel);
827 const TargetSchedModel *SchedModel;
833 Context(C), SchedModel(nullptr), TRI(nullptr) {}
  /external/llvm/lib/Target/AArch64/
AArch64StorePairSuppress.cpp 34 TargetSchedModel SchedModel;
84 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx);
126 SchedModel.init(*ST.getSchedModel(), &ST, TII);
133 if (!SchedModel.hasInstrSchedModel()) {
AArch64ConditionalCompares.cpp 726 const MCSchedModel *SchedModel;
848 unsigned DelayLimit = SchedModel->MispredictPenalty * 3 / 4;
896 SchedModel =
  /external/llvm/include/llvm/MC/
MCInstrItineraries.h 113 const MCSchedModel *SchedModel; ///< Basic machine properties.
121 InstrItineraryData() : SchedModel(&MCSchedModel::DefaultSchedModel),
127 : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F),
128 Itineraries(SchedModel->InstrItineraries) {}
  /external/llvm/lib/Target/Hexagon/
HexagonMachineScheduler.h 47 const TargetSchedModel *SchedModel;
58 SchedModel(SM), TotalPackets(0) {
65 Packet.resize(SchedModel->getIssueWidth());
135 const TargetSchedModel *SchedModel;
156 DAG(nullptr), SchedModel(nullptr), Available(ID, Name+".A"),
169 SchedModel = smodel;
192 const TargetSchedModel *SchedModel;
207 : DAG(nullptr), SchedModel(nullptr), Top(TopQID, "TopQ"),
  /external/llvm/lib/CodeGen/
EarlyIfConversion.cpp 583 const MCSchedModel *SchedModel;
691 unsigned CritLimit = SchedModel->MispredictPenalty/2;
787 SchedModel =
IfConversion.cpp 159 TargetSchedModel SchedModel;
280 SchedModel.init(*ST.getSchedModel(), &ST, TII);
687 unsigned NumCycles = SchedModel.computeInstrLatency(&*I, false);
    [all...]
  /external/llvm/lib/Target/ARM/
ARMSubtarget.h 227 /// SchedModel - Processor specific instruction costs.
228 const MCSchedModel *SchedModel;

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