1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the TargetRegisterInfo interface. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetRegisterInfo.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/CodeGen/MachineFunction.h" 17 #include "llvm/CodeGen/MachineRegisterInfo.h" 18 #include "llvm/CodeGen/VirtRegMap.h" 19 #include "llvm/Support/raw_ostream.h" 20 21 using namespace llvm; 22 23 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 24 regclass_iterator RCB, regclass_iterator RCE, 25 const char *const *SRINames, 26 const unsigned *SRILaneMasks, 27 unsigned SRICoveringLanes) 28 : InfoDesc(ID), SubRegIndexNames(SRINames), 29 SubRegIndexLaneMasks(SRILaneMasks), 30 RegClassBegin(RCB), RegClassEnd(RCE), 31 CoveringLanes(SRICoveringLanes) { 32 } 33 34 TargetRegisterInfo::~TargetRegisterInfo() {} 35 36 void PrintReg::print(raw_ostream &OS) const { 37 if (!Reg) 38 OS << "%noreg"; 39 else if (TargetRegisterInfo::isStackSlot(Reg)) 40 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); 41 else if (TargetRegisterInfo::isVirtualRegister(Reg)) 42 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg); 43 else if (TRI && Reg < TRI->getNumRegs()) 44 OS << '%' << TRI->getName(Reg); 45 else 46 OS << "%physreg" << Reg; 47 if (SubIdx) { 48 if (TRI) 49 OS << ':' << TRI->getSubRegIndexName(SubIdx); 50 else 51 OS << ":sub(" << SubIdx << ')'; 52 } 53 } 54 55 void PrintRegUnit::print(raw_ostream &OS) const { 56 // Generic printout when TRI is missing. 57 if (!TRI) { 58 OS << "Unit~" << Unit; 59 return; 60 } 61 62 // Check for invalid register units. 63 if (Unit >= TRI->getNumRegUnits()) { 64 OS << "BadUnit~" << Unit; 65 return; 66 } 67 68 // Normal units have at least one root. 69 MCRegUnitRootIterator Roots(Unit, TRI); 70 assert(Roots.isValid() && "Unit has no roots."); 71 OS << TRI->getName(*Roots); 72 for (++Roots; Roots.isValid(); ++Roots) 73 OS << '~' << TRI->getName(*Roots); 74 } 75 76 void PrintVRegOrUnit::print(raw_ostream &OS) const { 77 if (TRI && TRI->isVirtualRegister(Unit)) { 78 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit); 79 return; 80 } 81 PrintRegUnit::print(OS); 82 } 83 84 /// getAllocatableClass - Return the maximal subclass of the given register 85 /// class that is alloctable, or NULL. 86 const TargetRegisterClass * 87 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { 88 if (!RC || RC->isAllocatable()) 89 return RC; 90 91 const unsigned *SubClass = RC->getSubClassMask(); 92 for (unsigned Base = 0, BaseE = getNumRegClasses(); 93 Base < BaseE; Base += 32) { 94 unsigned Idx = Base; 95 for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) { 96 unsigned Offset = countTrailingZeros(Mask); 97 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset); 98 if (SubRC->isAllocatable()) 99 return SubRC; 100 Mask >>= Offset; 101 Idx += Offset + 1; 102 } 103 } 104 return nullptr; 105 } 106 107 /// getMinimalPhysRegClass - Returns the Register Class of a physical 108 /// register of the given type, picking the most sub register class of 109 /// the right type that contains this physreg. 110 const TargetRegisterClass * 111 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { 112 assert(isPhysicalRegister(reg) && "reg must be a physical register"); 113 114 // Pick the most sub register class of the right type that contains 115 // this physreg. 116 const TargetRegisterClass* BestRC = nullptr; 117 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){ 118 const TargetRegisterClass* RC = *I; 119 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && 120 (!BestRC || BestRC->hasSubClass(RC))) 121 BestRC = RC; 122 } 123 124 assert(BestRC && "Couldn't find the register class"); 125 return BestRC; 126 } 127 128 /// getAllocatableSetForRC - Toggle the bits that represent allocatable 129 /// registers for the specific register class. 130 static void getAllocatableSetForRC(const MachineFunction &MF, 131 const TargetRegisterClass *RC, BitVector &R){ 132 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); 133 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); 134 for (unsigned i = 0; i != Order.size(); ++i) 135 R.set(Order[i]); 136 } 137 138 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, 139 const TargetRegisterClass *RC) const { 140 BitVector Allocatable(getNumRegs()); 141 if (RC) { 142 // A register class with no allocatable subclass returns an empty set. 143 const TargetRegisterClass *SubClass = getAllocatableClass(RC); 144 if (SubClass) 145 getAllocatableSetForRC(MF, SubClass, Allocatable); 146 } else { 147 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), 148 E = regclass_end(); I != E; ++I) 149 if ((*I)->isAllocatable()) 150 getAllocatableSetForRC(MF, *I, Allocatable); 151 } 152 153 // Mask out the reserved registers 154 BitVector Reserved = getReservedRegs(MF); 155 Allocatable &= Reserved.flip(); 156 157 return Allocatable; 158 } 159 160 static inline 161 const TargetRegisterClass *firstCommonClass(const uint32_t *A, 162 const uint32_t *B, 163 const TargetRegisterInfo *TRI) { 164 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32) 165 if (unsigned Common = *A++ & *B++) 166 return TRI->getRegClass(I + countTrailingZeros(Common)); 167 return nullptr; 168 } 169 170 const TargetRegisterClass * 171 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A, 172 const TargetRegisterClass *B) const { 173 // First take care of the trivial cases. 174 if (A == B) 175 return A; 176 if (!A || !B) 177 return nullptr; 178 179 // Register classes are ordered topologically, so the largest common 180 // sub-class it the common sub-class with the smallest ID. 181 return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this); 182 } 183 184 const TargetRegisterClass * 185 TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 186 const TargetRegisterClass *B, 187 unsigned Idx) const { 188 assert(A && B && "Missing register class"); 189 assert(Idx && "Bad sub-register index"); 190 191 // Find Idx in the list of super-register indices. 192 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI) 193 if (RCI.getSubReg() == Idx) 194 // The bit mask contains all register classes that are projected into B 195 // by Idx. Find a class that is also a sub-class of A. 196 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this); 197 return nullptr; 198 } 199 200 const TargetRegisterClass *TargetRegisterInfo:: 201 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, 202 const TargetRegisterClass *RCB, unsigned SubB, 203 unsigned &PreA, unsigned &PreB) const { 204 assert(RCA && SubA && RCB && SubB && "Invalid arguments"); 205 206 // Search all pairs of sub-register indices that project into RCA and RCB 207 // respectively. This is quadratic, but usually the sets are very small. On 208 // most targets like X86, there will only be a single sub-register index 209 // (e.g., sub_16bit projecting into GR16). 210 // 211 // The worst case is a register class like DPR on ARM. 212 // We have indices dsub_0..dsub_7 projecting into that class. 213 // 214 // It is very common that one register class is a sub-register of the other. 215 // Arrange for RCA to be the larger register so the answer will be found in 216 // the first iteration. This makes the search linear for the most common 217 // case. 218 const TargetRegisterClass *BestRC = nullptr; 219 unsigned *BestPreA = &PreA; 220 unsigned *BestPreB = &PreB; 221 if (RCA->getSize() < RCB->getSize()) { 222 std::swap(RCA, RCB); 223 std::swap(SubA, SubB); 224 std::swap(BestPreA, BestPreB); 225 } 226 227 // Also terminate the search one we have found a register class as small as 228 // RCA. 229 unsigned MinSize = RCA->getSize(); 230 231 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) { 232 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); 233 for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) { 234 // Check if a common super-register class exists for this index pair. 235 const TargetRegisterClass *RC = 236 firstCommonClass(IA.getMask(), IB.getMask(), this); 237 if (!RC || RC->getSize() < MinSize) 238 continue; 239 240 // The indexes must compose identically: PreA+SubA == PreB+SubB. 241 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); 242 if (FinalA != FinalB) 243 continue; 244 245 // Is RC a better candidate than BestRC? 246 if (BestRC && RC->getSize() >= BestRC->getSize()) 247 continue; 248 249 // Yes, RC is the smallest super-register seen so far. 250 BestRC = RC; 251 *BestPreA = IA.getSubReg(); 252 *BestPreB = IB.getSubReg(); 253 254 // Bail early if we reached MinSize. We won't find a better candidate. 255 if (BestRC->getSize() == MinSize) 256 return BestRC; 257 } 258 } 259 return BestRC; 260 } 261 262 // Compute target-independent register allocator hints to help eliminate copies. 263 void 264 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, 265 ArrayRef<MCPhysReg> Order, 266 SmallVectorImpl<MCPhysReg> &Hints, 267 const MachineFunction &MF, 268 const VirtRegMap *VRM) const { 269 const MachineRegisterInfo &MRI = MF.getRegInfo(); 270 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 271 272 // Hints with HintType != 0 were set by target-dependent code. 273 // Such targets must provide their own implementation of 274 // TRI::getRegAllocationHints to interpret those hint types. 275 assert(Hint.first == 0 && "Target must implement TRI::getRegAllocationHints"); 276 277 // Target-independent hints are either a physical or a virtual register. 278 unsigned Phys = Hint.second; 279 if (VRM && isVirtualRegister(Phys)) 280 Phys = VRM->getPhys(Phys); 281 282 // Check that Phys is a valid hint in VirtReg's register class. 283 if (!isPhysicalRegister(Phys)) 284 return; 285 if (MRI.isReserved(Phys)) 286 return; 287 // Check that Phys is in the allocation order. We shouldn't heed hints 288 // from VirtReg's register class if they aren't in the allocation order. The 289 // target probably has a reason for removing the register. 290 if (std::find(Order.begin(), Order.end(), Phys) == Order.end()) 291 return; 292 293 // All clear, tell the register allocator to prefer this register. 294 Hints.push_back(Phys); 295 } 296
