1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the Mips specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef MIPSSUBTARGET_H 15 #define MIPSSUBTARGET_H 16 17 #include "MipsFrameLowering.h" 18 #include "MipsISelLowering.h" 19 #include "MipsInstrInfo.h" 20 #include "MipsJITInfo.h" 21 #include "MipsSelectionDAGInfo.h" 22 #include "llvm/IR/DataLayout.h" 23 #include "llvm/MC/MCInstrItineraries.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Target/TargetSubtargetInfo.h" 26 #include <string> 27 28 #define GET_SUBTARGETINFO_HEADER 29 #include "MipsGenSubtargetInfo.inc" 30 31 namespace llvm { 32 class StringRef; 33 34 class MipsTargetMachine; 35 36 class MipsSubtarget : public MipsGenSubtargetInfo { 37 virtual void anchor(); 38 39 public: 40 // NOTE: O64 will not be supported. 41 enum MipsABIEnum { 42 UnknownABI, O32, N32, N64, EABI 43 }; 44 45 protected: 46 enum MipsArchEnum { 47 Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64, 48 Mips64r2, Mips64r6 49 }; 50 51 // Mips architecture version 52 MipsArchEnum MipsArchVersion; 53 54 // Mips supported ABIs 55 MipsABIEnum MipsABI; 56 57 // IsLittle - The target is Little Endian 58 bool IsLittle; 59 60 // IsSingleFloat - The target only supports single precision float 61 // point operations. This enable the target to use all 32 32-bit 62 // floating point registers instead of only using even ones. 63 bool IsSingleFloat; 64 65 // IsFPXX - MIPS O32 modeless ABI. 66 bool IsFPXX; 67 68 // IsFP64bit - The target processor has 64-bit floating point registers. 69 bool IsFP64bit; 70 71 /// Are odd single-precision registers permitted? 72 /// This corresponds to -modd-spreg and -mno-odd-spreg 73 bool UseOddSPReg; 74 75 // IsNan2008 - IEEE 754-2008 NaN encoding. 76 bool IsNaN2008bit; 77 78 // IsFP64bit - General-purpose registers are 64 bits wide 79 bool IsGP64bit; 80 81 // HasVFPU - Processor has a vector floating point unit. 82 bool HasVFPU; 83 84 // CPU supports cnMIPS (Cavium Networks Octeon CPU). 85 bool HasCnMips; 86 87 // isLinux - Target system is Linux. Is false we consider ELFOS for now. 88 bool IsLinux; 89 90 // UseSmallSection - Small section is used. 91 bool UseSmallSection; 92 93 /// Features related to the presence of specific instructions. 94 95 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32 96 bool HasMips3_32; 97 98 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2 99 bool HasMips3_32r2; 100 101 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32 102 bool HasMips4_32; 103 104 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2 105 bool HasMips4_32r2; 106 107 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2 108 bool HasMips5_32r2; 109 110 // InMips16 -- can process Mips16 instructions 111 bool InMips16Mode; 112 113 // Mips16 hard float 114 bool InMips16HardFloat; 115 116 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode 117 bool PreviousInMips16Mode; 118 119 // InMicroMips -- can process MicroMips instructions 120 bool InMicroMipsMode; 121 122 // HasDSP, HasDSPR2 -- supports DSP ASE. 123 bool HasDSP, HasDSPR2; 124 125 // Allow mixed Mips16 and Mips32 in one source file 126 bool AllowMixed16_32; 127 128 // Optimize for space by compiling all functions as Mips 16 unless 129 // it needs floating point. Functions needing floating point are 130 // compiled as Mips32 131 bool Os16; 132 133 // HasMSA -- supports MSA ASE. 134 bool HasMSA; 135 136 InstrItineraryData InstrItins; 137 138 // Relocation Model 139 Reloc::Model RM; 140 141 // We can override the determination of whether we are in mips16 mode 142 // as from the command line 143 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode; 144 145 MipsTargetMachine *TM; 146 147 Triple TargetTriple; 148 149 const DataLayout DL; // Calculates type size & alignment 150 const MipsSelectionDAGInfo TSInfo; 151 MipsJITInfo JITInfo; 152 std::unique_ptr<const MipsInstrInfo> InstrInfo; 153 std::unique_ptr<const MipsFrameLowering> FrameLowering; 154 std::unique_ptr<const MipsTargetLowering> TLInfo; 155 std::unique_ptr<const MipsInstrInfo> InstrInfo16; 156 std::unique_ptr<const MipsFrameLowering> FrameLowering16; 157 std::unique_ptr<const MipsTargetLowering> TLInfo16; 158 std::unique_ptr<const MipsInstrInfo> InstrInfoSE; 159 std::unique_ptr<const MipsFrameLowering> FrameLoweringSE; 160 std::unique_ptr<const MipsTargetLowering> TLInfoSE; 161 162 public: 163 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 164 AntiDepBreakMode& Mode, 165 RegClassVector& CriticalPathRCs) const override; 166 167 /// Only O32 and EABI supported right now. 168 bool isABI_EABI() const { return MipsABI == EABI; } 169 bool isABI_N64() const { return MipsABI == N64; } 170 bool isABI_N32() const { return MipsABI == N32; } 171 bool isABI_O32() const { return MipsABI == O32; } 172 bool isABI_FPXX() const { return false; } // TODO: add check for FPXX 173 unsigned getTargetABI() const { return MipsABI; } 174 175 /// This constructor initializes the data members to match that 176 /// of the specified triple. 177 MipsSubtarget(const std::string &TT, const std::string &CPU, 178 const std::string &FS, bool little, Reloc::Model RM, 179 MipsTargetMachine *TM); 180 181 /// ParseSubtargetFeatures - Parses features string setting specified 182 /// subtarget options. Definition of function is auto generated by tblgen. 183 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 184 185 bool hasMips1() const { return MipsArchVersion >= Mips1; } 186 bool hasMips2() const { return MipsArchVersion >= Mips2; } 187 bool hasMips3() const { return MipsArchVersion >= Mips3; } 188 bool hasMips4() const { return MipsArchVersion >= Mips4; } 189 bool hasMips5() const { return MipsArchVersion >= Mips5; } 190 bool hasMips4_32() const { return HasMips4_32; } 191 bool hasMips4_32r2() const { return HasMips4_32r2; } 192 bool hasMips32() const { 193 return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 && 194 MipsArchVersion != Mips4 && MipsArchVersion != Mips5; 195 } 196 bool hasMips32r2() const { 197 return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 || 198 MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6; 199 } 200 bool hasMips32r6() const { 201 return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6; 202 } 203 bool hasMips64() const { return MipsArchVersion >= Mips64; } 204 bool hasMips64r2() const { 205 return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6; 206 } 207 bool hasMips64r6() const { return MipsArchVersion == Mips64r6; } 208 209 bool hasCnMips() const { return HasCnMips; } 210 211 bool isLittle() const { return IsLittle; } 212 bool isFPXX() const { return IsFPXX; } 213 bool isFP64bit() const { return IsFP64bit; } 214 bool useOddSPReg() const { return UseOddSPReg; } 215 bool isNaN2008() const { return IsNaN2008bit; } 216 bool isNotFP64bit() const { return !IsFP64bit; } 217 bool isGP64bit() const { return IsGP64bit; } 218 bool isGP32bit() const { return !IsGP64bit; } 219 bool isSingleFloat() const { return IsSingleFloat; } 220 bool isNotSingleFloat() const { return !IsSingleFloat; } 221 bool hasVFPU() const { return HasVFPU; } 222 bool inMips16Mode() const { 223 switch (OverrideMode) { 224 case NoOverride: 225 return InMips16Mode; 226 case Mips16Override: 227 return true; 228 case NoMips16Override: 229 return false; 230 } 231 llvm_unreachable("Unexpected mode"); 232 } 233 bool inMips16ModeDefault() const { 234 return InMips16Mode; 235 } 236 bool inMips16HardFloat() const { 237 return inMips16Mode() && InMips16HardFloat; 238 } 239 bool inMicroMipsMode() const { return InMicroMipsMode; } 240 bool hasDSP() const { return HasDSP; } 241 bool hasDSPR2() const { return HasDSPR2; } 242 bool hasMSA() const { return HasMSA; } 243 bool isLinux() const { return IsLinux; } 244 bool useSmallSection() const { return UseSmallSection; } 245 246 bool hasStandardEncoding() const { return !inMips16Mode(); } 247 248 bool mipsSEUsesSoftFloat() const; 249 250 bool enableLongBranchPass() const { 251 return hasStandardEncoding() || allowMixed16_32(); 252 } 253 254 /// Features related to the presence of specific instructions. 255 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); } 256 257 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } 258 bool allowMixed16_32() const { return inMips16ModeDefault() | 259 AllowMixed16_32;} 260 261 bool os16() const { return Os16;}; 262 263 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } 264 bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); } 265 266 // for now constant islands are on for the whole compilation unit but we only 267 // really use them if in addition we are in mips16 mode 268 static bool useConstantIslands(); 269 270 unsigned stackAlignment() const { return hasMips64() ? 16 : 8; } 271 272 // Grab relocation model 273 Reloc::Model getRelocationModel() const {return RM;} 274 275 /// \brief Reset the subtarget for the Mips target. 276 void resetSubtarget(MachineFunction *MF); 277 278 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS, 279 const TargetMachine *TM); 280 281 /// Does the system support unaligned memory access. 282 /// 283 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not 284 /// specify which component of the system provides it. Hardware, software, and 285 /// hybrid implementations are all valid. 286 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); } 287 288 // Set helper classes 289 void setHelperClassesMips16(); 290 void setHelperClassesMipsSE(); 291 292 MipsJITInfo *getJITInfo() { return &JITInfo; } 293 const MipsSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; } 294 const DataLayout *getDataLayout() const { return &DL; } 295 const MipsInstrInfo *getInstrInfo() const { return InstrInfo.get(); } 296 const TargetFrameLowering *getFrameLowering() const { 297 return FrameLowering.get(); 298 } 299 const MipsRegisterInfo *getRegisterInfo() const { 300 return &InstrInfo->getRegisterInfo(); 301 } 302 const MipsTargetLowering *getTargetLowering() const { return TLInfo.get(); } 303 }; 304 } // End llvm namespace 305 306 #endif 307
