| /external/clang/test/CodeGen/ |
| transparent-union.c | 13 // CHECK-LABEL: define void @f1_0(i32* %a0)
17 void f1_0(int *a0) {
19 f0(a0);
20 f0p(a0);
23 void f1_1(int *a0) {
24 f0((transp_t0) { a0 });
|
| mips-byval-arg.c | 10 // O32-LABEL: define void @foo1(i32 %a0.coerce0, i32 %a0.coerce1, i32 %a0.coerce2)
11 // N64-LABEL: define void @foo1(i64 %a0.coerce0, i32 %a0.coerce1)
13 void foo1(S0 a0) {
14 foo2(a0);
|
| x86_32-arguments-realign.c | 8 void f0(struct s0 a0) {
10 f0_g0 = a0.a;
|
| arm-vector-arguments.c | 13 int8x16x2_t f0(int8x16_t a0, int8x16_t a1) {
14 return vzipq_s8(a0, a1);
25 T_float32x2 f1_0(T_float32x2 a0) { return a0; }
27 T_float32x4 f1_1(T_float32x4 a0) { return a0; }
29 T_float32x8 f1_2(T_float32x8 a0) { return a0; }
31 T_float32x16 f1_3(T_float32x16 a0) { return a0; }
[all...] |
| le32-libcall-pow.c | 13 void test_pow(float a0, double a1, long double a2) {
15 float l0 = powf(a0, a0);
|
| _Bool-conversion.c | 7 static _Bool f0_0(void *a0) { return (_Bool) a0; }
|
| mips64-padding-arg.c | 12 // N64-LABEL: define void @foo1(i32 %a0, i64, double %a1.coerce0, i64 %a1.coerce1, i64 %a1.coerce2, i64 %a1.coerce3, double %a2.coerce0, i64 %a2.coerce1, i64 %a2.coerce2, i64 %a2.coerce3, i32 %b, i64, double %a3.coerce0, i64 %a3.coerce1, i64 %a3.coerce2, i64 %a3.coerce3)
13 // N64: tail call void @foo2(i32 1, i32 2, i32 %a0, i64 undef, double %a1.coerce0, i64 %a1.coerce1, i64 %a1.coerce2, i64 %a1.coerce3, double %a2.coerce0, i64 %a2.coerce1, i64 %a2.coerce2, i64 %a2.coerce3, i32 3, i64 undef, double %a3.coerce0, i64 %a3.coerce1, i64 %a3.coerce2, i64 %a3.coerce3)
18 void foo1(int a0, S0 a1, S0 a2, int b, S0 a3) {
19 foo2(1, 2, a0, a1, a2, 3, a3);
24 // N64-LABEL: define void @foo3(i32 %a0, i64, fp128 %a1)
25 // N64: tail call void @foo4(i32 1, i32 2, i32 %a0, i64 undef, fp128 %a1)
30 void foo3(int a0, long double a1) {
31 foo4(1, 2, a0, a1);
36 // N64-LABEL: define void @foo5(%struct.S0* noalias sret %agg.result, i64, fp128 %a0)
37 // N64: call void @foo6(%struct.S0* sret %agg.result, i32 1, i32 2, i64 undef, fp128 %a0)
[all...] |
| bitfield-2.c | 24 int f0_load(struct s0 *a0) {
26 return a0->f0;
28 int f0_store(struct s0 *a0) {
29 return (a0->f0 = 1);
31 int f0_reload(struct s0 *a0) {
32 return (a0->f0 += 1);
70 int f1_load(struct s1 *a0) {
72 return a0->f1;
74 int f1_store(struct s1 *a0) {
75 return (a0->f1 = 1234)
[all...] |
| mips64-class-return.cpp | 37 // CHECK-LABEL: define void @_Z4foo32D2(i64 %a0.coerce0, double %a0.coerce1)
38 void foo3(D2 a0) {
39 gd2 = a0;
42 // CHECK-LABEL: define void @_Z4foo42D0(i64 %a0.coerce0, i64 %a0.coerce1)
43 void foo4(D0 a0) {
44 gd0 = a0;
|
| x86_32-arguments-win32.c | 4 // CHECK-LABEL: define void @f1_2(%struct.s1* byval align 4 %a0)
10 void f1_2(struct s1 a0) {}
39 void f5_2(struct s5 a0) {}
42 // CHECK-LABEL: define void @f6_2(%struct.s6* byval align 4 %a0)
47 void f6_2(struct s6 a0) {}
|
| /development/ndk/sources/android/libportable/arch-mips/ |
| _setjmp.S | 70 REG_S v0, JB_MAGIC(a0)
71 REG_S s0, JB_S0(a0)
72 REG_S s1, JB_S1(a0)
73 REG_S s2, JB_S2(a0)
74 REG_S s3, JB_S3(a0)
75 REG_S s4, JB_S4(a0)
76 REG_S s5, JB_S5(a0)
77 REG_S s6, JB_S6(a0)
78 REG_S s7, JB_S7(a0)
79 REG_S s8, JB_S8(a0)
[all...] |
| setjmp.S | 68 REG_S a0, A0OFF(sp)
70 move a0, zero # get current signal mask
76 REG_L a0, A0OFF(sp) # restore jmpbuf
78 REG_S ra, JB_PC(a0) # sc_pc = return address
84 REG_S v0, JB_MAGIC(a0)
85 REG_S s0, JB_S0(a0)
86 REG_S s1, JB_S1(a0)
87 REG_S s2, JB_S2(a0)
88 REG_S s3, JB_S3(a0)
89 REG_S s4, JB_S4(a0)
[all...] |
| /external/qemu/distrib/sdl-1.2.15/src/video/ataricommon/ |
| SDL_atarieddi.S | 36 movel sp@(4),a0 /* Value of EdDI cookie */
40 jsr (a0)
|
| /external/clang/test/CodeGenCXX/ |
| template-anonymous-union-member-initializer.cpp | 11 A<int> a0; variable
|
| /external/clang/test/Sema/ |
| PR2919-builtin-types-compat-strips-crv.c | 6 int a0[__builtin_types_compatible_p(T0, variable
|
| weak-import-on-enum.c | 7 a0 enumerator in enum:A
|
| /external/pixman/pixman/ |
| pixman-mips-memcpy-asm.S | 53 move v0, a0 /* memcpy returns the dst pointer */
56 xor t8, a1, a0
57 andi t8, t8, 0x3 /* t8 is a0/a1 word-displacement */
60 negu a3, a0
62 andi a3, a3, 0x3 /* we need to copy a3 bytes to make a0/a1 aligned */
63 beq a3, zero, $chk16w /* when a3=0 then the dst (a0) is word-aligned */
68 SWHI t8, 0(a0)
69 addu a0, a0, a3
79 addu a3, a0, a3 /* Now a3 is the final dst after 64-byte chunks *
[all...] |
| /bionic/libc/arch-mips/bionic/ |
| _setjmp.S | 57 REG_S v0, SC_REGS+ZERO*REGSZ(a0)
58 REG_S s0, SC_REGS+S0*REGSZ(a0)
59 REG_S s1, SC_REGS+S1*REGSZ(a0)
60 REG_S s2, SC_REGS+S2*REGSZ(a0)
61 REG_S s3, SC_REGS+S3*REGSZ(a0)
62 REG_S s4, SC_REGS+S4*REGSZ(a0)
63 REG_S s5, SC_REGS+S5*REGSZ(a0)
64 REG_S s6, SC_REGS+S6*REGSZ(a0)
65 REG_S s7, SC_REGS+S7*REGSZ(a0)
66 REG_S s8, SC_REGS+S8*REGSZ(a0)
[all...] |
| setjmp.S | 55 REG_S a0, A0OFF(sp)
57 move a0, zero # get current signal mask
63 REG_L a0, A0OFF(sp) # restore jmpbuf
65 REG_S ra, SC_PC(a0) # sc_pc = return address
71 REG_S v0, SC_REGS+ZERO*REGSZ(a0)
72 REG_S s0, SC_REGS+S0*REGSZ(a0)
73 REG_S s1, SC_REGS+S1*REGSZ(a0)
74 REG_S s2, SC_REGS+S2*REGSZ(a0)
75 REG_S s3, SC_REGS+S3*REGSZ(a0)
76 REG_S s4, SC_REGS+S4*REGSZ(a0)
[all...] |
| /bionic/libc/arch-mips64/bionic/ |
| _setjmp.S | 57 REG_S v0, SC_REGS+ZERO*REGSZ(a0)
58 REG_S s0, SC_REGS+S0*REGSZ(a0)
59 REG_S s1, SC_REGS+S1*REGSZ(a0)
60 REG_S s2, SC_REGS+S2*REGSZ(a0)
61 REG_S s3, SC_REGS+S3*REGSZ(a0)
62 REG_S s4, SC_REGS+S4*REGSZ(a0)
63 REG_S s5, SC_REGS+S5*REGSZ(a0)
64 REG_S s6, SC_REGS+S6*REGSZ(a0)
65 REG_S s7, SC_REGS+S7*REGSZ(a0)
66 REG_S s8, SC_REGS+S8*REGSZ(a0)
[all...] |
| setjmp.S | 55 REG_S a0, A0OFF(sp)
57 move a0, zero # get current signal mask
63 REG_L a0, A0OFF(sp) # restore jmpbuf
65 REG_S ra, SC_PC(a0) # sc_pc = return address
71 REG_S v0, SC_REGS+ZERO*REGSZ(a0)
72 REG_S s0, SC_REGS+S0*REGSZ(a0)
73 REG_S s1, SC_REGS+S1*REGSZ(a0)
74 REG_S s2, SC_REGS+S2*REGSZ(a0)
75 REG_S s3, SC_REGS+S3*REGSZ(a0)
76 REG_S s4, SC_REGS+S4*REGSZ(a0)
[all...] |
| /external/clang/test/CXX/expr/ |
| p8.cpp | 4 int a0; variable
15 f0(a0);
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-mips64.cc | 99 COMPARE(addu(a0, a1, a2),
100 "00a62021 addu a0, a1, a2");
101 COMPARE(daddu(a0, a1, a2),
102 "00a6202d daddu a0, a1, a2");
112 COMPARE(subu(a0, a1, a2),
113 "00a62023 subu a0, a1, a2");
114 COMPARE(dsubu(a0, a1, a2),
115 "00a6202f dsubu a0, a1, a2");
126 COMPARE(mult(a0, a1),
127 "00850018 mult a0, a1")
[all...] |
| /external/qemu/target-i386/ |
| mem_helper.c | 41 void helper_cmpxchg8b(CPUX86State *env, target_ulong a0)
47 d = cpu_ldq_data(env, a0);
49 cpu_stq_data(env, a0, ((uint64_t)ECX << 32) | (uint32_t)EBX);
53 cpu_stq_data(env, a0, d);
62 void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
67 if ((a0 & 0xf) != 0)
70 d0 = cpu_ldq_data(env, a0);
71 d1 = cpu_ldq_data(env, a0 + 8);
73 cpu_stq_data(env, a0, EBX);
74 cpu_stq_data(env, a0 + 8, ECX)
[all...] |
| /external/chromium_org/third_party/libvpx/source/libvpx/vp8/common/mips/dspr2/ |
| reconinter_dspr2.c | 34 unsigned int a0, a1, a2, a3; local
43 "ulw %[a0], 0(%[src]) \n\t"
47 "sw %[a0], 0(%[dst]) \n\t"
51 : [a0] "=&r" (a0), [a1] "=&r" (a1),
69 unsigned int a0, a1; local
78 "ulw %[a0], 0(%[src]) \n\t"
80 "sw %[a0], 0(%[dst]) \n\t"
82 : [a0] "=&r" (a0), [a1] "=&r" (a1
99 unsigned int a0, a1; local
[all...] |
