/external/chromium_org/v8/test/cctest/ |
test-utils-arm64.cc | 267 void Clobber(MacroAssembler* masm, RegList reg_list, uint64_t const value) { 270 if (reg_list & (1UL << i)) { 290 void ClobberFP(MacroAssembler* masm, RegList reg_list, double const value) { 293 if (reg_list & (1UL << i)) { 309 void Clobber(MacroAssembler* masm, CPURegList reg_list) { 310 if (reg_list.type() == CPURegister::kRegister) { 312 Clobber(masm, reg_list.list()); 313 } else if (reg_list.type() == CPURegister::kFPRegister) { 315 ClobberFP(masm, reg_list.list());
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test-utils-arm64.h | 221 void Clobber(MacroAssembler* masm, RegList reg_list, 225 void ClobberFP(MacroAssembler* masm, RegList reg_list, 231 void Clobber(MacroAssembler* masm, CPURegList reg_list);
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/external/vixl/test/ |
test-utils-a64.cc | 267 void Clobber(MacroAssembler* masm, RegList reg_list, uint64_t const value) { 270 if (reg_list & (UINT64_C(1) << i)) { 290 void ClobberFP(MacroAssembler* masm, RegList reg_list, double const value) { 293 if (reg_list & (UINT64_C(1) << i)) { 309 void Clobber(MacroAssembler* masm, CPURegList reg_list) { 310 if (reg_list.type() == CPURegister::kRegister) { 312 Clobber(masm, reg_list.list()); 313 } else if (reg_list.type() == CPURegister::kFPRegister) { 315 ClobberFP(masm, reg_list.list());
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test-utils-a64.h | 216 void Clobber(MacroAssembler* masm, RegList reg_list, 220 void ClobberFP(MacroAssembler* masm, RegList reg_list, 226 void Clobber(MacroAssembler* masm, CPURegList reg_list);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
R600GenRegisterInfo.pl | 174 my @reg_list; 181 $reg_list[$i] = $name; 183 return @reg_list;
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SIGenRegisterInfo.pl | 283 my $reg_list = join(', ', @registers); 285 print "def $class_prefix\_$reg_width : RegisterClass<\"AMDGPU\", [" . join (', ', @types) . "], $reg_width,\n (add $reg_list)\n>{\n";
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/external/mesa3d/src/gallium/drivers/radeon/ |
R600GenRegisterInfo.pl | 174 my @reg_list; 181 $reg_list[$i] = $name; 183 return @reg_list;
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SIGenRegisterInfo.pl | 283 my $reg_list = join(', ', @registers); 285 print "def $class_prefix\_$reg_width : RegisterClass<\"AMDGPU\", [" . join (', ', @types) . "], $reg_width,\n (add $reg_list)\n>{\n";
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/system/core/libpixelflinger/codeflinger/ |
ARMAssemblerProxy.cpp | 236 void ARMAssemblerProxy::LDM(int cc, int dir, int Rn, int W, uint32_t reg_list) { 237 mTarget->LDM(cc, dir, Rn, W, reg_list); 239 void ARMAssemblerProxy::STM(int cc, int dir, int Rn, int W, uint32_t reg_list) { 240 mTarget->STM(cc, dir, Rn, W, reg_list);
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ARMAssembler.h | 134 int Rn, int W, uint32_t reg_list); 136 int Rn, int W, uint32_t reg_list);
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ARMAssemblerProxy.h | 121 int Rn, int W, uint32_t reg_list); 123 int Rn, int W, uint32_t reg_list);
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ARMAssembler.cpp | 332 int Rn, int W, uint32_t reg_list) 337 (uint32_t(U[dir])<<23) | (1<<20) | (W<<21) | (Rn<<16) | reg_list; 341 int Rn, int W, uint32_t reg_list) 346 (uint32_t(U[dir])<<23) | (0<<20) | (W<<21) | (Rn<<16) | reg_list;
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ARMAssemblerInterface.h | 173 int Rn, int W, uint32_t reg_list) = 0; 175 int Rn, int W, uint32_t reg_list) = 0;
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Arm64Assembler.h | 151 int Rn, int W, uint32_t reg_list); 153 int Rn, int W, uint32_t reg_list);
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Arm64Assembler.cpp | 682 int Rn, int W, uint32_t reg_list) 693 if((reg_list & (1 << i))) 703 int Rn, int W, uint32_t reg_list) 714 if((reg_list & (1 << i))) [all...] |
MIPSAssembler.h | 133 int Rn, int W, uint32_t reg_list); 135 int Rn, int W, uint32_t reg_list);
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MIPSAssembler.cpp | 974 int Rn, int W, uint32_t reg_list) 979 // (uint32_t(U[dir])<<23) | (1<<20) | (W<<21) | (Rn<<16) | reg_list; 986 int Rn, int W, uint32_t reg_list) 991 // (uint32_t(U[dir])<<23) | (0<<20) | (W<<21) | (Rn<<16) | reg_list; [all...] |
/system/core/libpixelflinger/tests/arch-arm64/assembler/ |
arm64_assembler_test.cpp | 751 uint32_t reg_list[] = {0,1,12,14}; local [all...] |
/art/compiler/dex/quick/arm/ |
codegen_arm.h | 215 static constexpr ResourceMask EncodeArmRegList(int reg_list); 216 static constexpr ResourceMask EncodeArmRegFpcsList(int reg_list);
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target_arm.cc | 149 constexpr ResourceMask ArmMir2Lir::EncodeArmRegList(int reg_list) { 150 return ResourceMask::RawMask(static_cast<uint64_t >(reg_list), 0u); 153 constexpr ResourceMask ArmMir2Lir::EncodeArmRegFpcsList(int reg_list) { 154 return ResourceMask::RawMask(static_cast<uint64_t >(reg_list) << kArmFPReg16, 0u);
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