| /external/llvm/lib/Target/Mips/ |
| MipsSERegisterInfo.cpp | 186 unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
193 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
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| MipsSEFrameLowering.cpp | 290 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
382 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO)
408 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
419 BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
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| MipsSEInstrInfo.cpp | 94 Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
365 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
372 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
598 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
606 // addu $ra, $v0, $zero
607 // addu $sp, $sp, $v1
610 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), T9)
612 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA
[all...] |
| MipsSEISelDAGToDAG.cpp | 179 // addu $v1, $v0, $t9
184 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
197 // 2. addu $globalbasereg, $2, $t9
207 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
211 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
246 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
654 Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
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| MipsLongBranch.cpp | 284 // addu $at, $ra, $at
325 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
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| MipsAsmPrinter.cpp | 942 EmitInstrRegRegReg(Mips::ADDu, Mips::S2, Mips::RA, Mips::ZERO);
[all...] |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsTargetStreamer.cpp | 532 // addu $gp, $gp, $reg
569 TmpInst.setOpcode(Mips::ADDu);
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
