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Searched
refs:CP0_Status
(Results
1 - 7
of
7
) sorted by null
/external/qemu/hw/mips/
mips_int.c
11
if ((env->
CP0_Status
& (1 << CP0St_IE)) &&
12
!(env->
CP0_Status
& (1 << CP0St_EXL)) &&
13
!(env->
CP0_Status
& (1 << CP0St_ERL)) &&
15
if ((env->
CP0_Status
& env->CP0_Cause & CP0Ca_IP_mask) &&
/external/qemu/target-mips/
helper.c
50
if (!(env->
CP0_Status
& (1 << CP0St_ERL)))
116
int UX = (env->
CP0_Status
& (1 << CP0St_UX)) != 0;
117
int SX = (env->
CP0_Status
& (1 << CP0St_SX)) != 0;
118
int KX = (env->
CP0_Status
& (1 << CP0St_KX)) != 0;
128
if (unlikely(env->
CP0_Status
& (1 << CP0St_ERL))) {
643
if (!(env->
CP0_Status
& (1 << CP0St_EXL)))
651
env->
CP0_Status
|= (1 << CP0St_SR);
655
env->
CP0_Status
|= (1 << CP0St_NMI);
665
env->
CP0_Status
|= (1 << CP0St_ERL) | (1 << CP0St_BEV);
668
if (!(env->
CP0_Status
& (1 << CP0St_EXL))
[
all
...]
cpu.h
275
int32_t
CP0_Status
;
461
uint32_t CP0_Status_rw_bitmask; /* Read/write bits in
CP0_Status
*/
523
return ((env->
CP0_Status
&
542
if (!(env->
CP0_Status
& (1 << CP0St_IE)) ||
543
(env->
CP0_Status
& (1 << CP0St_EXL)) ||
544
(env->
CP0_Status
& (1 << CP0St_ERL)) ||
551
status = env->
CP0_Status
& CP0Ca_IP_mask;
op_helper.c
38
if (!(env->
CP0_Status
& (1 << CP0St_EXL)) &&
39
!(env->
CP0_Status
& (1 << CP0St_ERL)) &&
41
env->hflags |= (env->
CP0_Status
>> CP0St_KSU) & MIPS_HFLAG_KSU;
45
(env->
CP0_Status
& (1 << CP0St_PX)) ||
46
(env->
CP0_Status
& (1 << CP0St_UX))) {
49
if (env->
CP0_Status
& (1 << CP0St_UX)) {
53
if ((env->
CP0_Status
& (1 << CP0St_CU0)) ||
57
if (env->
CP0_Status
& (1 << CP0St_CU1)) {
60
if (env->
CP0_Status
& (1 << CP0St_FR)) {
76
if (env->
CP0_Status
& (1 << CP0St_CU3))
[
all
...]
machine.c
115
qemu_put_sbe32s(f, &env->
CP0_Status
);
266
qemu_get_sbe32s(f, &env->
CP0_Status
);
translate.c
[
all
...]
/external/qemu/
gdbstub.c
989
if (env->
CP0_Status
& (1 << CP0St_FR))
1000
case 32: GET_REGL((int32_t)env->
CP0_Status
);
1041
if (env->
CP0_Status
& (1 << CP0St_FR))
1061
case 32: env->
CP0_Status
= tmp; break;
[
all
...]
Completed in 144 milliseconds