| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 314 BSWAP, CTTZ, CTLZ, CTPOP,
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| IntegerDivision.cpp | 183 Function *CTLZ = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz,
242 // ; %tmp0 = tail call i32 @llvm.ctlz.i32(i32 %divisor, i1 true)
243 // ; %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %dividend, i1 true)
255 Value *Tmp0 = Builder.CreateCall2(CTLZ, Divisor, True);
256 Value *Tmp1 = Builder.CreateCall2(CTLZ, Dividend, True);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 288 case ISD::CTLZ: return "ctlz";
|
| LegalizeVectorTypes.cpp | 71 case ISD::CTLZ:
586 case ISD::CTLZ:
[all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeVectorOps.cpp | 259 case ISD::CTLZ:
[all...] |
| LegalizeIntegerTypes.cpp | 62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
[all...] |
| DAGCombiner.cpp | [all...] |
| TargetLowering.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 123 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
124 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 158 setOperationAction(ISD::CTLZ, VT, Expand);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 158 setOperationAction(ISD::CTLZ, VT, Expand);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 239 setOperationAction(ISD::CTLZ, MVT::i16, Legal);
240 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
241 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 497 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
498 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
506 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
507 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 259 setOperationAction(ISD::CTLZ, Ty, Legal);
[all...] |
| MipsISelLowering.cpp | 368 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
370 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 260 setOperationAction(ISD::CTLZ, VT, Expand);
324 setOperationAction(ISD::CTLZ, VT, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 208 // We have native support for a 64-bit CTLZ, via FLOGR.
209 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
210 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 641 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
643 // These just redirect to CTTZ and CTLZ on ARM.
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 464 setOperationAction(ISD::CTLZ, VT, Expand);
[all...] |
