| /art/compiler/utils/ |
| assembler_thumb_test.cc | 412 __ mov(R3, ShifterOperand(R4, LSR, 5));
419 __ mov(R8, ShifterOperand(R4, LSR, 5));
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| debug-arm64.cc | 166 __ Lsr(scratch, reg, 32);
|
| regexp-macro-assembler-arm64.cc | 298 __ Lsr(x11, GetCachedRegister(start_reg), kWRegSizeInBits);
427 __ Lsr(x11, GetCachedRegister(start_reg), kWRegSizeInBits);
827 __ Add(input_length, start_offset(), Operand(w10, LSR, 1));
837 __ Lsr(capture_end.X(), capture_start.X(), kWRegSizeInBits);
[all...] |
| macro-assembler-arm64-inl.h | 906 void MacroAssembler::Lsr(const Register& rd,
911 lsr(rd, rn, shift);
915 void MacroAssembler::Lsr(const Register& rd,
[all...] |
| macro-assembler-arm64.h | 442 inline void Lsr(const Register& rd, const Register& rn, unsigned shift);
443 inline void Lsr(const Register& rd, const Register& rn, const Register& rm);
[all...] |
| lithium-codegen-arm64.cc | [all...] |
| macro-assembler-arm64.cc | 465 return Operand(dst, LSR, shift_high);
[all...] |
| code-stubs-arm64.cc | [all...] |
| full-codegen-arm64.cc | [all...] |
| /art/compiler/utils/arm/ |
| assembler_arm.h | 585 virtual void Lsr(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
596 virtual void Lsr(Register rd, Register rm, Register rn, bool setcc = false,
|
| assembler_arm32.h | 202 void Lsr(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
213 void Lsr(Register rd, Register rm, Register rn, bool setcc = false,
|
| assembler_thumb2.h | 233 void Lsr(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
244 void Lsr(Register rd, Register rm, Register rn, bool setcc = false,
|
| assembler_arm32.cc | [all...] |
| assembler_thumb2.cc | 843 case LSR: thumb_opcode = 0b01; break;
1098 case LSR: opcode = 0b01; break;
1118 case LSR: opcode = 0b01; break;
[all...] |
| /external/chromium_org/v8/src/compiler/arm64/ |
| code-generator-arm64.cc | 283 ASSEMBLE_SHIFT(Lsr, 64);
286 ASSEMBLE_SHIFT(Lsr, 32);
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombine.h | 351 Value *SimplifyShrShlDemandedBits(Instruction *Lsr, Instruction *Sftl,
|
| /external/vixl/src/a64/ |
| macro-assembler-a64.h | 785 void Lsr(const Register& rd, const Register& rn, unsigned shift) {
789 lsr(rd, rn, shift);
791 void Lsr(const Register& rd, const Register& rn, const Register& rm) {
[all...] |
| /external/chromium_org/v8/test/cctest/ |
| test-assembler-arm64.cc | 299 __ Mvn(w4, Operand(w0, LSR, 3));
300 __ Mvn(x5, Operand(x1, LSR, 4));
372 __ Mov(w15, Operand(w11, LSR, 3));
373 __ Mov(x18, Operand(x12, LSR, 4));
529 __ Orr(x5, x0, Operand(x1, LSR, 4));
626 __ Orn(x5, x0, Operand(x1, LSR, 1));
695 __ And(x5, x0, Operand(x1, LSR, 1));
770 __ Ands(w0, w0, Operand(w1, LSR, 4));
824 __ Bic(x5, x0, Operand(x1, LSR, 1));
910 __ Bics(w0, w0, Operand(w0, LSR, 1))
[all...] |
| /external/vixl/test/ |
| test-assembler-a64.cc | 264 __ Mvn(w4, Operand(w0, LSR, 3));
265 __ Mvn(x5, Operand(x1, LSR, 4));
430 __ Mov(w15, Operand(w11, LSR, 3));
431 __ Mov(x18, Operand(x12, LSR, 4));
489 __ Orr(x5, x0, Operand(x1, LSR, 4));
578 __ Orn(x5, x0, Operand(x1, LSR, 1));
645 __ And(x5, x0, Operand(x1, LSR, 1));
718 __ Ands(w0, w0, Operand(w1, LSR, 4));
771 __ Bic(x5, x0, Operand(x1, LSR, 1));
855 __ Bics(w0, w0, Operand(w0, LSR, 1))
[all...] |
| /art/compiler/optimizing/ |
| code_generator_arm.cc | [all...] |
