| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 121 Opc = Mips::MTC1;
301 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
304 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
310 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
547 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
554 // mtc1 Lo, $fp
563 // mtc1 Lo, $fp
564 // mtc1 Hi, $fp + 1
|
| MipsFastISel.cpp | 328 EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
|
| MipsAsmPrinter.cpp | 735 // Because of the current td files for Mips32, the operands for MTC1
739 if (Opcode == Mips::MTC1) {
775 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
[all...] |
| /external/chromium_org/v8/src/mips/ |
| constants-mips.h | 449 MTC1 = ((0 << 3) + 4) << 21,
|
| simulator-mips.cc | [all...] |
| assembler-mips.cc | 2010 void Assembler::mtc1(Register rt, FPURegister fs) { function in class:v8::Assembler
[all...] |
| /external/chromium_org/v8/src/mips64/ |
| constants-mips64.h | 461 MTC1 = ((0 << 3) + 4) << 21,
|
| simulator-mips64.cc | [all...] |
| assembler-mips64.cc | 2226 void Assembler::mtc1(Register rt, FPURegister fs) { function in class:v8::Assembler
[all...] |
| /external/pcre/dist/sljit/ |
| sljitNativeMIPS_common.c | 151 #define MTC1 (HI(17) | (4 << 21))
[all...] |
| /external/valgrind/main/none/tests/mips32/ |
| MoveIns.stdout.exp | 29 MTC1
30 mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
31 mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
32 mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
33 mtc1 $t4, $f3 :: fs 0.000000, rt 0x0
34 mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
35 mtc1 $t6, $f5 :: fs 0.000000, rt 0x0
36 mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
37 mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
38 mtc1 $v1, $f8 :: fs nan, rt 0xfffffff
[all...] |
