| /external/llvm/lib/Target/AArch64/ |
| AArch64ConditionalCompares.cpp | 66 STATISTIC(NumMultNZCVUses, "Number of ccmps rejected (NZCV used)");
67 STATISTIC(NumUnknNZCVDefs, "Number of ccmps rejected (NZCV def unknown)");
102 // operand that specifies the NZCV flag values when the condition is false and
125 // ccmp w1, #17, 4, ne ; 4 = nZcv
303 if (!I->readsRegister(AArch64::NZCV)) {
354 MIOperands(I).analyzePhysReg(AArch64::NZCV, TRI);
382 // Reject any live-in physregs. It's probably NZCV/EFLAGS, and very hard to
425 if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) {
646 // The NZCV immediate operand should provide flags for the case where Head
649 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(CmpBBTailCC)
[all...] |
| AArch64InstrInfo.cpp | 318 // if NZCV is used, do not fold.
319 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
345 // if NZCV is used, do not fold.
346 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
630 // Replace SUBSWrr with SUBWrr if NZCV is not used.
706 // Replace SUBSWrr with SUBWrr if NZCV is not used.
707 int Cmp_NZCV = CmpInstr->findRegisterDefOperandIdx(AArch64::NZCV, true);
755 // basic block, to check whether NZCV is used or modified in between.
768 // Check that NZCV isn't set between the comparison instruction and the one we
774 if (Instr.modifiesRegister(AArch64::NZCV, TRI) |
[all...] |
| AArch64ISelLowering.cpp | 220 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
[all...] |
| /external/chromium_org/v8/test/cctest/ |
| test-assembler-arm64.cc | 181 __ Msr(NZCV, xzr); \
[all...] |
| test-utils-arm64.cc | 391 __ Mrs(tmp, NZCV);
|
| test-disasm-arm64.cc | [all...] |
| /external/vixl/test/ |
| test-assembler-a64.cc | [all...] |
| test-utils-a64.cc | 389 __ Mrs(tmp, NZCV);
|
| test-simulator-a64.cc | 562 __ Mrs(flags, NZCV);
601 // Each NZCV result only requires 4 bits.
682 __ Mrs(flags, NZCV);
717 // Each NZCV result only requires 4 bits.
[all...] |
| test-disasm-a64.cc | [all...] |
| /external/chromium_org/v8/src/arm64/ |
| simulator-arm64.cc | 86 case NZCV:
399 nzcv_ = SimSystemRegister::DefaultValueFor(NZCV);
863 nzcv().SetN(N);
864 nzcv().SetZ(Z);
865 nzcv().SetC(C);
866 nzcv().SetV(V);
867 LogSystemRegister(NZCV);
885 nzcv().C());
981 nzcv().SetRawValue(FPUnorderedFlag);
983 nzcv().SetRawValue(FPLessThanFlag)
[all...] |
| disasm-arm64.cc | 1162 case NZCV: form = "'Xt, nzcv"; break;
1171 case NZCV: form = "nzcv, 'Xt"; break;
1440 int nzcv = (instr->Nzcv() << Flags_offset); local
[all...] |
| constants-arm64.h | 173 V_(Nzcv, 3, 0, Bits) \
208 /* NZCV */ \
214 M_(NZCV, Flags_mask) \
379 NZCV = ((0x1 << SysO0_offset) |
[all...] |
| macro-assembler-arm64.cc | 350 StatusFlags nzcv,
358 ConditionalCompareMacro(rn, temp, nzcv, cond, op);
365 ConditionalCompare(rn, operand, nzcv, cond, op);
373 ConditionalCompare(rn, temp, nzcv, cond, op);
[all...] |
| lithium-codegen-arm64.cc | 163 // nZCv (equal), nzCv (greater) or nzCV (unordered).
[all...] |
| /external/vixl/src/a64/ |
| disasm-a64.cc | 1434 int nzcv = (instr->Nzcv() << Flags_offset); local
[all...] |
| simulator-a64.cc | 51 case NZCV:
97 nzcv_ = SimSystemRegister::DefaultValueFor(NZCV);
286 nzcv().SetN(N);
287 nzcv().SetZ(Z);
288 nzcv().SetC(C);
289 nzcv().SetV(V);
380 nzcv().SetRawValue(FPUnorderedFlag);
382 nzcv().SetRawValue(FPLessThanFlag);
384 nzcv().SetRawValue(FPGreaterThanFlag);
386 nzcv().SetRawValue(FPEqualFlag)
[all...] |
| constants-a64.h | 97 V_(Nzcv, 3, 0, Bits) \
132 /* NZCV */ \
138 M_(NZCV, Flags_mask) \
269 NZCV = ((0x1 << SysO0_offset) |
[all...] |
| macro-assembler-a64.cc | 388 StatusFlags nzcv,
392 ConditionalCompareMacro(rn, -operand.immediate(), nzcv, cond, CCMN);
394 ConditionalCompareMacro(rn, operand, nzcv, cond, CCMP);
401 StatusFlags nzcv,
405 ConditionalCompareMacro(rn, -operand.immediate(), nzcv, cond, CCMP);
407 ConditionalCompareMacro(rn, operand, nzcv, cond, CCMN);
414 StatusFlags nzcv,
422 ConditionalCompare(rn, operand, nzcv, cond, op);
429 ConditionalCompare(rn, temp, nzcv, cond, op);
[all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 396 {"nzcv", NZCV},
|
| AArch64BaseInfo.h | 241 /// Given a condition code, return NZCV flags that would satisfy that condition.
246 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
765 NZCV = 0xda10, // 11 011 0100 0010 000
[all...] |
| /external/llvm/test/MC/AArch64/ |
| basic-a64-instructions.s | [all...] |
| /external/valgrind/main/none/tests/arm/ |
| v6intThumb.stdout.exp | 350 uxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
351 uxtb r1, r2 :: rd 0x00000097 rm 0x31415997, c:v-in 3, cpsr 0xf0000000 NZCV
359 sxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
360 sxtb r1, r2 :: rd 0xffffff97 rm 0x31415997, c:v-in 3, cpsr 0xf0000000 NZCV
368 uxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
369 uxth r1, r2 :: rd 0x00009597 rm 0x31419597, c:v-in 3, cpsr 0xf0000000 NZCV
377 sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
378 sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 3, cpsr 0xf0000000 NZCV
[all...] |
