| /external/llvm/lib/Target/Hexagon/ |
| HexagonCFGOptimizer.cpp | 76 int NewOpcode = 0;
79 NewOpcode = Hexagon::JMP_f;
83 NewOpcode = Hexagon::JMP_t;
87 NewOpcode = Hexagon::JMP_fnew_t;
91 NewOpcode = Hexagon::JMP_tnew_t;
98 MI->setDesc(QII->get(NewOpcode));
|
| HexagonVLIWPacketizer.cpp | 439 int NewOpcode;
441 NewOpcode = QII->GetDotNewPredOp(MI, MBPI);
443 NewOpcode = QII->GetDotNewOp(MI);
444 MI->setDesc(QII->get(NewOpcode));
451 int NewOpcode = QII->GetDotOldOp(MI->getOpcode());
452 MI->setDesc(QII->get(NewOpcode));
772 int NewOpcode = QII->GetDotNewOp(MI);
773 const MCInstrDesc &desc = QII->get(NewOpcode);
[all...] |
| HexagonInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 137 int NewOpcode;
139 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
145 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
146 BuildMI(MBB, II, dl, TII.get(NewOpcode))
152 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
|
| /external/llvm/lib/Target/R600/ |
| AMDILCFGStructurizer.cpp | 228 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
230 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
232 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
233 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
236 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
238 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum);
469 int NewOpcode, DebugLoc DL) {
471 ->CreateMachineInstr(TII->get(NewOpcode), DL);
478 int NewOpcode, DebugLoc DL) {
480 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL)
[all...] |
| SIISelLowering.cpp | [all...] |
| SIInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.cpp | 427 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
431 if (!NewOpcode) {
436 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
437 assert(NewOpcode && "No restore instruction available");
440 MBBI->setDesc(ZII->get(NewOpcode));
|
| SystemZInstrInfo.cpp | 49 // each having the opcode given by NewOpcode.
51 unsigned NewOpcode) const {
73 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
74 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
91 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
92 assert(NewOpcode && "No support for huge argument lists yet");
93 MI->setDesc(get(NewOpcode));
725 unsigned NewOpcode;
727 NewOpcode = SystemZ::RISBG;
729 NewOpcode = SystemZ::RISBMux
[all...] |
| SystemZInstrInfo.h | 118 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 180 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
181 if (NewOpcode != -1) {
184 Opcode = NewOpcode;
185 TmpInst.setOpcode (NewOpcode);
|
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 263 unsigned NewOpcode = 0;
270 NewOpcode = X86::CBW;
274 NewOpcode = X86::CWDE;
278 NewOpcode = X86::CDQE;
282 if (NewOpcode != 0) {
284 Inst.setOpcode(NewOpcode);
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCAsmPrinter.cpp | 669 unsigned NewOpcode =
673 EmitToStreamer(OutStreamer, MCInstBuilder(NewOpcode)
683 unsigned NewOpcode =
689 EmitToStreamer(OutStreamer, MCInstBuilder(NewOpcode)
[all...] |
| PPCRegisterInfo.cpp | 821 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
822 MI.setDesc(TII.get(NewOpcode));
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
