| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 86 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
89 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
90 MVT VT = Outs[i].VT;
91 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
100 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
103 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
104 MVT VT = Outs[i].VT;
105 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
118 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
120 unsigned NumOps = Outs.size()
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 94 Hexagon_CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
116 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
117 EVT VT = Outs[i].VT;
118 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
132 &Outs,
136 unsigned NumOps = Outs.size();
147 EVT ArgVT = Outs[i].VT;
148 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
|
| HexagonCallingConvLower.h | 83 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
88 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| HexagonISelLowering.h | 90 SmallVectorImpl<ISD::OutputArg> &Outs,
133 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| HexagonISelLowering.cpp | 317 const SmallVectorImpl<ISD::OutputArg> &Outs,
329 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
399 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
408 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
435 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
437 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
446 Outs, OutVals, Ins, DAG);
475 ISD::ArgFlagsTy Flags = Outs[i].Flags
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 129 const SmallVectorImpl<ISD::OutputArg> &Outs,
161 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| MSP430ISelLowering.cpp | 267 const SmallVectorImpl<ISD::OutputArg> &Outs) {
268 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
352 const SmallVectorImpl<ISD::OutputArg> &Outs) {
353 State.AnalyzeReturn(Outs, RetCC_MSP430);
396 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
414 Outs, OutVals, Ins, dl, DAG, InVals);
524 const SmallVectorImpl<ISD::OutputArg> &Outs,
532 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
540 AnalyzeReturnValues(CCInfo, RVLocs, Outs);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 123 const SmallVectorImpl<ISD::OutputArg> &Outs,
128 const SmallVectorImpl<ISD::OutputArg> &Outs,
133 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| SparcISelLowering.cpp | 173 const SmallVectorImpl<ISD::OutputArg> &Outs,
177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
184 const SmallVectorImpl<ISD::OutputArg> &Outs,
197 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
246 const SmallVectorImpl<ISD::OutputArg> &Outs,
257 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
687 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
703 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 139 const SmallVectorImpl<ISD::OutputArg> &Outs,
206 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 599 const SmallVectorImpl<ISD::OutputArg> &Outs,
605 const SmallVectorImpl<ISD::OutputArg> &Outs,
641 const SmallVectorImpl<ISD::OutputArg> &Outs,
650 const SmallVectorImpl<ISD::OutputArg> &Outs,
658 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 357 const SmallVectorImpl<ISD::OutputArg> &Outs,
376 const SmallVectorImpl<ISD::OutputArg> &Outs,
380 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.h | 52 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 360 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
372 void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
542 const SmallVectorImpl<ISD::OutputArg> &Outs,
547 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.h | 52 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 269 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
280 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 75 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
494 const SmallVectorImpl<ISD::OutputArg> &Outs,
551 if (Outs[OIdx].Flags.isByVal() == false) {
563 // update the index for Outs
571 assert((getValueType(Ty) == Outs[OIdx].VT ||
572 (getValueType(Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
592 unsigned align = Outs[OIdx].Flags.getByValAlign();
655 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
680 // Args.size() and Outs.size() need not match
[all...] |
| NVPTXISelLowering.h | 232 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 67 SmallVector<ISD::OutputArg, 4> Outs;
68 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
71 Outs, Fn->getContext());
|
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 109 SmallVectorImpl<MachineInstr*> &Outs);
361 SmallVectorImpl<MachineInstr*> &Outs) {
395 Outs.push_back(MI);
|
| ARMISelLowering.h | 544 const SmallVectorImpl<ISD::OutputArg> &Outs,
551 const SmallVectorImpl<ISD::OutputArg> &Outs,
557 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | [all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.h | 127 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 243 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
