| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | [all...] |
| SelectionDAGNodes.h | [all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 141 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
142 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
143 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
144 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand);
145 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, Expand);
146 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, Expand);
298 return DAG.getExtLoad(Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, DL, VT, Chain, Ptr,
[all...] |
| AMDGPUISelLowering.cpp | 218 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
221 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
224 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
227 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
[all...] |
| R600ISelLowering.cpp | 122 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 625 LD->getExtensionType() == ISD::SEXTLOAD) {
850 // Handle sign_extend and sextload.
861 LD->getExtensionType() != ISD::SEXTLOAD |
[all...] |
| HexagonISelLowering.cpp | 665 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 84 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
86 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 462 case ISD::SEXTLOAD: OS << ", sext"; break;
|
| DAGCombiner.cpp | [all...] |
| LegalizeVectorOps.cpp | 546 case ISD::SEXTLOAD:
[all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 208 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
| NVPTXISelDAGToDAG.cpp | 432 // Sign : ISD::SEXTLOAD
440 if ((LD->getExtensionType() == ISD::SEXTLOAD))
658 // Sign : ISD::SEXTLOAD
669 if (ExtensionType == ISD::SEXTLOAD)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 221 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| PPCISelLowering.cpp | 82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
476 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 132 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
134 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 227 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
378 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMISelLowering.cpp | 409 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
574 setLoadExtAction(ISD::SEXTLOAD, Tys[i], Legal);
589 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 470 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
[all...] |
