| /external/llvm/lib/Target/AArch64/ |
| AArch64AddressTypePromotion.cpp | 14 // d = sext i32 a to i64
18 // f = sext i32 b to i64
24 // Moreover, the current heuristic is simple: it does not create new sext
25 // operations, i.e., it gives up when a sext would have forked (e.g., if
82 // sext instructions.
104 /// Check if it is profitable to move a sext through this instruction.
107 /// - Inst has only one operand that will require a sext operation (we do
108 /// do not create new sext operation).
111 /// Check if it is possible and legal to move a sext through this
115 /// - Other sext operation
[all...] |
| AArch64TargetTransformInfo.cpp | 168 ImmVal = Imm.sext((BitSize + 63) & ~0x3fU);
226 case Instruction::SExt:
|
| /external/llvm/unittests/IR/ |
| AttributesTest.cpp | 26 AttributeSet::get(C, 2, Attribute::SExt)
39 AttributeSet::get(C, 1, Attribute::SExt)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonRemoveSZExtArgs.cpp | 60 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt)) {
|
| HexagonISelLowering.cpp | 124 LocInfo = CCValAssign::SExt;
162 LocInfo = CCValAssign::SExt;
237 LocInfo = CCValAssign::SExt;
480 // Loc info must be one of Full, SExt, ZExt, or AExt.
484 case CCValAssign::SExt:
[all...] |
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | [all...] |
| Analysis.cpp | 547 } else if (CallerAttrs.contains(Attribute::SExt)) {
548 if (!CalleeAttrs.contains(Attribute::SExt))
552 CallerAttrs.removeAttribute(Attribute::SExt);
553 CalleeAttrs.removeAttribute(Attribute::SExt);
|
| TargetLoweringBase.cpp | [all...] |
| BasicTargetTransformInfo.cpp | 415 // Assume that sext is done using SHL and SRA.
416 if (Opcode == Instruction::SExt)
|
| /external/llvm/include/llvm/Target/ |
| TargetCallingConv.h | 30 static const uint64_t SExt = 1ULL<<1; ///< Sign extended
66 bool isSExt() const { return Flags & SExt; }
|
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 35 SExt, // The value is sign extended in the location.
146 return (HTP == AExt || HTP == SExt || HTP == ZExt);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreLowerThreadLocal.cpp | 109 case Instruction::SExt:
|
| /external/llvm/lib/Transforms/ObjCARC/ |
| ObjCARCUtil.cpp | 223 case Instruction::SExt: case Instruction::ZExt: case Instruction::Trunc:
|
| /external/llvm/include/llvm/IR/ |
| Attributes.h | 100 SExt, ///< Sign extended before/after call
|
| /external/llvm/lib/IR/ |
| Instructions.cpp | [all...] |
| Attributes.cpp | 218 if (hasAttribute(Attribute::SExt))
362 case Attribute::SExt: return 1 << 1;
[all...] |
| Instruction.cpp | 232 case SExt: return "sext";
|
| ConstantFold.cpp | 514 // sext(undef) = 0, because the top bits will all be the same.
516 if (opc == Instruction::ZExt || opc == Instruction::SExt ||
669 case Instruction::SExt:
673 CI->getValue().sext(BitWidth));
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCasts.cpp | 166 C = ConstantExpr::getIntegerCast(C, Ty, isSigned /*Sext or ZExt*/);
196 case Instruction::SExt:
206 Opc == Instruction::SExt);
284 // If this is a vector sext from a compare, then we don't want to break the
286 if (opc == Instruction::SExt && isa<CmpInst>(V) && Ty->isVectorTy())
412 case Instruction::SExt:
674 case Instruction::SExt: // zext(sext(x)) -> sext(x).
[all...] |
| InstCombineVectorOps.cpp | 631 case Instruction::SExt:
716 case Instruction::SExt:
793 case Instruction::SExt:
[all...] |
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 444 case Instruction::SExt:
|
| /external/llvm/lib/Transforms/Scalar/ |
| LoopRotation.cpp | 224 case Instruction::SExt:
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 311 LocInfo = CCValAssign::SExt;
472 if (VA.getLocInfo() == CCValAssign::SExt)
611 case CCValAssign::SExt:
[all...] |
| /external/llvm/lib/Target/CppBackend/ |
| CPPBackend.cpp | 494 HANDLE_ATTR(SExt);
846 case Instruction::SExt: Out << "Instruction::SExt"; break;
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 872 // stack slot and 4-byte store/load sequence. Or just sext the 4-byte
[all...] |
