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    Searched refs:SI_CONFIG_REG_OFFSET (Results 1 - 8 of 8) sorted by null

  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeonsi/
radeonsi_pm4.c 60 if (reg >= SI_CONFIG_REG_OFFSET && reg <= SI_CONFIG_REG_END) {
62 reg -= SI_CONFIG_REG_OFFSET;
si_state_streamout.c 165 cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - SI_CONFIG_REG_OFFSET) >> 2;
r600_hw_context.c 681 cs->buf[cs->cdw++] = (R_0085F0_CP_COHER_CNTL - SI_CONFIG_REG_OFFSET) >> 2;
685 cs->buf[cs->cdw++] = (R_0085F8_CP_COHER_BASE - SI_CONFIG_REG_OFFSET) >> 2;
sid.h 28 #define SI_CONFIG_REG_OFFSET 0x00008000
    [all...]
  /external/mesa3d/src/gallium/drivers/radeonsi/
radeonsi_pm4.c 60 if (reg >= SI_CONFIG_REG_OFFSET && reg <= SI_CONFIG_REG_END) {
62 reg -= SI_CONFIG_REG_OFFSET;
si_state_streamout.c 165 cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - SI_CONFIG_REG_OFFSET) >> 2;
r600_hw_context.c 681 cs->buf[cs->cdw++] = (R_0085F0_CP_COHER_CNTL - SI_CONFIG_REG_OFFSET) >> 2;
685 cs->buf[cs->cdw++] = (R_0085F8_CP_COHER_BASE - SI_CONFIG_REG_OFFSET) >> 2;
sid.h 28 #define SI_CONFIG_REG_OFFSET 0x00008000
    [all...]

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