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    Searched refs:SI_CONTEXT_REG_OFFSET (Results 1 - 8 of 8) sorted by null

  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeonsi/
si_state_streamout.c 72 16*i - SI_CONTEXT_REG_OFFSET) >> 2;
186 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
190 cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
194 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
radeonsi_pm4.c 68 } else if (reg >= SI_CONTEXT_REG_OFFSET && reg <= SI_CONTEXT_REG_END) {
70 reg -= SI_CONTEXT_REG_OFFSET;
r600_hw_context.c 653 cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - SI_CONTEXT_REG_OFFSET) >> 2;
657 cs->buf[cs->cdw++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - SI_CONTEXT_REG_OFFSET) >> 2;
sid.h 32 #define SI_CONTEXT_REG_OFFSET 0x00028000
    [all...]
  /external/mesa3d/src/gallium/drivers/radeonsi/
si_state_streamout.c 72 16*i - SI_CONTEXT_REG_OFFSET) >> 2;
186 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
190 cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
194 cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
radeonsi_pm4.c 68 } else if (reg >= SI_CONTEXT_REG_OFFSET && reg <= SI_CONTEXT_REG_END) {
70 reg -= SI_CONTEXT_REG_OFFSET;
r600_hw_context.c 653 cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - SI_CONTEXT_REG_OFFSET) >> 2;
657 cs->buf[cs->cdw++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - SI_CONTEXT_REG_OFFSET) >> 2;
sid.h 32 #define SI_CONTEXT_REG_OFFSET 0x00028000
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