/system/core/libpixelflinger/codeflinger/ |
ARMAssemblerInterface.h | 209 virtual void SMLAL(int cc, int xy, 317 SMLAL(cc, xyBB, RdHi, RdLo, Rs, Rm); } 320 SMLAL(cc, xyTB, RdHi, RdLo, Rs, Rm); } 323 SMLAL(cc, xyBT, RdHi, RdLo, Rs, Rm); } 326 SMLAL(cc, xyTT, RdHi, RdLo, Rs, Rm); }
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ARMAssemblerProxy.cpp | 281 void ARMAssemblerProxy::SMLAL( int cc, int xy, 283 mTarget->SMLAL(cc, xy, RdHi, RdLo, Rs, Rm);
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ARMAssembler.h | 154 virtual void SMLAL(int cc, int xy,
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ARMAssemblerProxy.h | 141 virtual void SMLAL(int cc, int xy,
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Arm64Assembler.h | 171 virtual void SMLAL(int cc, int xy,
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ARMAssembler.cpp | 420 void ARMAssembler::SMLAL(int cc, int xy,
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MIPSAssembler.h | 153 virtual void SMLAL(int cc, int xy,
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Arm64Assembler.cpp | 820 void ArmToArm64Assembler::SMLAL(int /*cc*/, int /*xy*/, [all...] |
MIPSAssembler.cpp | [all...] |
/external/tremolo/Tremolo/ |
mdctARM.s | 329 SMLAL r8, r9, r6, r10 @ (r8, r9) += s0*T[0] 335 SMLAL r8, r12,r6, r11 @ (r8, r12) -= s0*T[1] 353 SMLAL r8, r9, r7, r11 @ (r8, r9) += s2*T[0] 359 SMLAL r8, r12,r6, r11 @ (r8, r12) -= s0*T[0] 389 SMLAL r14,r12,r9, r10 @ (r14,r12) += ro2*T[0] 395 SMLAL r14,r3, r8, r10 @ (r14,r3) -= ro0*T[0] 406 SMLAL r14,r12,r7, r11 @ (r14,r12) += ri2*T[1] 412 SMLAL r14,r3, r6, r11 @ (r14,r3) -= ri0*T[1] 502 SMLAL r4, r3, r11,r10 @ (r4, r3) += s1*T[0] 505 SMLAL r11,r4, r2, r10 @ (r11,r4) += s0*T[0 [all...] |
/external/llvm/test/MC/ARM/ |
mul-v4.s | 1 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher 23 @ ARMV4: smlal r2, r3, r0, r1 @ encoding: [0x90,0x21,0xe3,0xe0] 27 smlal r2,r3,r0,r1 label
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basic-arm-instructions.s | [all...] |
basic-thumb2-instructions.s | [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.h | 171 SMLAL, // 64bit Signed Accumulate Multiply
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ARMISelDAGToDAG.cpp | [all...] |
ARMISelLowering.cpp | 578 // ARM and Thumb2 support UMLAL/SMLAL. [all...] |
/external/llvm/test/MC/AArch64/ |
arm64-advsimd.s | [all...] |
/external/valgrind/main/none/tests/arm/ |
v6intARM.stdout.exp | [all...] |
v6media.stdout.exp | 46 SMLAL 47 smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 48 smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 49 smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 50 smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 51 smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 52 smlal r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000 53 smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000 54 smlal r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000 55 smlal r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00 (…) [all...] |