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  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
brw_gs.h 88 struct brw_reg SVBI;
brw_gs_emit.c 50 * - The thread will be spawned with the "SVBI Payload Enable" bit set, so GRF
67 c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
374 get_element_ud(c->reg.SVBI, 0), brw_imm_ud(num_verts));
377 get_element_ud(c->reg.SVBI, 4));
380 /* Compute the destination indices to write to. Usually we use SVBI[0]
385 * in order SVBI[0] + (0, 2, 1) if we're using the first provoking
386 * vertex convention, and in order SVBI[0] + (1, 0, 2) if we're using
390 * packed-word execution mode, and SVBI is a double-word, we need to
392 * or (1, 0, 2)) to the destination_indices register, and then add SVBI
422 c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0))
    [all...]
  /external/mesa3d/src/mesa/drivers/dri/i965/
brw_gs.h 88 struct brw_reg SVBI;
brw_gs_emit.c 50 * - The thread will be spawned with the "SVBI Payload Enable" bit set, so GRF
67 c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
374 get_element_ud(c->reg.SVBI, 0), brw_imm_ud(num_verts));
377 get_element_ud(c->reg.SVBI, 4));
380 /* Compute the destination indices to write to. Usually we use SVBI[0]
385 * in order SVBI[0] + (0, 2, 1) if we're using the first provoking
386 * vertex convention, and in order SVBI[0] + (1, 0, 2) if we're using
390 * packed-word execution mode, and SVBI is a double-word, we need to
392 * or (1, 0, 2)) to the destination_indices register, and then add SVBI
422 c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0))
    [all...]

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