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    Searched refs:SuperRC (Results 1 - 8 of 8) sorted by null

  /external/llvm/lib/Target/R600/
SIInstrInfo.h 31 const TargetRegisterClass *SuperRC,
37 const TargetRegisterClass *SuperRC,
AMDGPUISelDAGToDAG.cpp 140 const TargetRegisterClass *SuperRC = TM.getRegisterInfo()->getRegClass(RCID);
144 return TM.getRegisterInfo()->getSubClassWithSubReg(SuperRC, SubRegIdx);
SIInstrInfo.cpp 781 const TargetRegisterClass *SuperRC,
787 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
808 const TargetRegisterClass *SuperRC,
821 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
    [all...]
  /external/llvm/lib/CodeGen/
AggressiveAntiDepBreaker.cpp 610 const TargetRegisterClass *SuperRC =
613 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
621 if (RenameOrder.count(SuperRC) == 0)
622 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
624 unsigned OrigR = RenameOrder[SuperRC];
690 RenameOrder.erase(SuperRC);
691 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
    [all...]
RegAllocGreedy.cpp     [all...]
TargetLoweringBase.cpp     [all...]
MachineVerifier.cpp     [all...]
  /external/llvm/utils/TableGen/
CodeGenRegisters.h 263 // classes SuperRC such that:
265 // R:SubRegIndex in this RC for all R in SuperRC.
333 CodeGenRegisterClass *SuperRC) {
334 SuperRegClasses[SubIdx].insert(SuperRC);

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