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Searched
refs:VEX
(Results
1 - 7
of
7
) sorted by null
/external/valgrind/main/
Android.mk
58
external/valgrind/main/
VEX
/pub \
97
VEX
/priv/main_globals.c \
98
VEX
/priv/main_main.c \
99
VEX
/priv/main_util.c \
100
VEX
/priv/ir_defs.c \
101
VEX
/priv/ir_match.c \
102
VEX
/priv/ir_opt.c \
103
VEX
/priv/ir_inject.c \
104
VEX
/priv/guest_generic_bb_to_IR.c \
105
VEX
/priv/guest_generic_x87.c
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/external/valgrind/
merge.upstream.sh
22
vex_svn_url="svn://svn.valgrind.org/
vex
/trunk"
26
vex_dir=$valgrind_dir/
VEX
29
vex_revision=`cat $current_dir/upstream.revs.txt | grep "
vex
: " | sed "s/
vex
: //"`
33
echo "
vex
: $vex_revision"
37
echo "Expecting 'val: <revision number>' and '
vex
: <revision number>'"
46
echo "
vex
: $upstream_vex_revision"
55
echo "Merging
vex
... (in $vex_dir)" | tee -a $current_dir/merge.log
61
echo "
vex
: $upstream_vex_revision" >> $current_dir/upstream.revs.txt
/external/llvm/lib/Target/X86/MCTargetDesc/
X86BaseInfo.h
378
// XOPA - Prefix to encode 0xA in
VEX
.MMMM of XOP instructions.
456
//
VEX
- encoding using 0xC4/0xC5
457
VEX
= 1,
472
///
VEX
- The opcode prefix used by AVX instructions
485
/// operand 3 with
VEX
.vvvv.
493
/// VEX_L - Stands for a bit in the
VEX
opcode prefix meaning the current
499
// VEX_LIG - Specifies that this instruction ignores the L-bit in the
VEX
508
// - 11 LIG (but, in insn encoding, leave
VEX
.L and EVEX.L in zeros.
X86MCCodeEmitter.cpp
81
// In the
VEX
prefix, registers are seen sequencially from 0-15 and encoded
85
//
VEX
.VVVV => XMM9 => ~9
611
/// called
VEX
.
651
// VEX_5M (
VEX
m-mmmmm field):
663
// VEX_4V (
VEX
vvvv field): a register specifier
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/external/llvm/utils/TableGen/
X86RecognizableInstr.cpp
114
VEX
= 1, XOP = 2, EVEX = 3
238
// Special case since there is no attribute class for 64-bit and
VEX
273
errs() << "Don't support
VEX
.L if EVEX_L2 is enabled: " << Name << "\n";
274
llvm_unreachable("Don't support
VEX
.L if EVEX_L2 is enabled");
359
} else if (Encoding == X86Local::
VEX
|| Encoding == X86Local::XOP) {
564
// - In AVX, there is a register operand in the
VEX
.vvvv field here -
577
// in ModRMVEX and the one above the one in the
VEX
.VVVV field
586
// - In AVX, there is a register operand in the
VEX
.vvvv field here -
601
// in ModRMVEX and the one above the one in the
VEX
.VVVV field
610
// - In AVX, there is a register operand in the
VEX
.vvvv field here
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...]
/external/llvm/lib/Target/X86/
X86CodeEmitter.cpp
702
// In the
VEX
prefix, registers are seen sequencially from 0-15 and encoded
706
//
VEX
.VVVV => XMM9 => ~9
781
// VEX_5M (
VEX
m-mmmmm field):
793
// VEX_4V (
VEX
vvvv field): a register specifier
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...]
/external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/tests/
avx.asm
195
; blendvpd doesn't have
vex
-encoded version of implicit xmm0
209
; blendvps doesn't have
vex
-encoded version of implicit xmm0
1295
; implicit XMM0 cannot be
VEX
encoded
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Completed in 288 milliseconds