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Searched
refs:active_fpu
(Results
1 - 6
of
6
) sorted by null
/external/qemu/target-mips/
op_helper.c
64
if (env->
active_fpu
.fcr0 & (1 << FCR0_F64)) {
[
all
...]
machine.c
52
save_fpu(f, &env->
active_fpu
);
202
load_fpu(f, &env->
active_fpu
);
translate_init.c
526
memcpy(&env->
active_fpu
, &env->fpus[0], sizeof(env->
active_fpu
));
translate.c
604
tcg_gen_ld_i32(t, cpu_env, offsetof(CPUMIPSState,
active_fpu
.fpr[reg].w[FP_ENDIAN_IDX]));
609
tcg_gen_st_i32(t, cpu_env, offsetof(CPUMIPSState,
active_fpu
.fpr[reg].w[FP_ENDIAN_IDX]));
614
tcg_gen_ld_i32(t, cpu_env, offsetof(CPUMIPSState,
active_fpu
.fpr[reg].w[!FP_ENDIAN_IDX]));
619
tcg_gen_st_i32(t, cpu_env, offsetof(CPUMIPSState,
active_fpu
.fpr[reg].w[!FP_ENDIAN_IDX]));
625
tcg_gen_ld_i64(t, cpu_env, offsetof(CPUMIPSState,
active_fpu
.fpr[reg].d));
640
tcg_gen_st_i64(t, cpu_env, offsetof(CPUMIPSState,
active_fpu
.fpr[reg].d));
[
all
...]
cpu.h
183
CPUMIPSFPUContext
active_fpu
;
member in struct:CPUMIPSState
/external/qemu/
gdbstub.c
990
GET_REGL(env->
active_fpu
.fpr[n - 38].d);
992
GET_REGL(env->
active_fpu
.fpr[n - 38].w[FP_ENDIAN_IDX]);
995
case 70: GET_REGL((int32_t)env->
active_fpu
.fcr31);
996
case 71: GET_REGL((int32_t)env->
active_fpu
.fcr0);
1026
set_float_rounding_mode(ieee_rm[env->
active_fpu
.fcr31 & 3], &env->
active_fpu
.fp_status)
1042
env->
active_fpu
.fpr[n - 38].d = tmp;
1044
env->
active_fpu
.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
1048
env->
active_fpu
.fcr31 = tmp & 0xFF83FFFF;
1053
SET_FP_ENABLE(env->
active_fpu
.fcr31, 0)
[
all
...]
Completed in 690 milliseconds