| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
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| cpu-features.h | 95 #ifndef cpu_has_llsc
96 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) macro
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| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
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| cpu-features.h | 95 #ifndef cpu_has_llsc
96 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) macro
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| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
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| cpu-features.h | 95 #ifndef cpu_has_llsc
96 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) macro
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| /prebuilts/ndk/9/platforms/android-12/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
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| cpu-features.h | 95 #ifndef cpu_has_llsc
96 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) macro
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| /prebuilts/ndk/9/platforms/android-13/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
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| cpu-features.h | 95 #ifndef cpu_has_llsc
96 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) macro
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| /prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
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| cpu-features.h | 95 #ifndef cpu_has_llsc
96 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) macro
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| /prebuilts/ndk/9/platforms/android-15/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
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| cpu-features.h | 95 #ifndef cpu_has_llsc
96 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) macro
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| /prebuilts/ndk/9/platforms/android-16/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
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| cpu-features.h | 95 #ifndef cpu_has_llsc
96 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) macro
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| /prebuilts/ndk/9/platforms/android-17/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
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| cpu-features.h | 95 #ifndef cpu_has_llsc
96 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) macro
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| /prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
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| cpu-features.h | 95 #ifndef cpu_has_llsc
96 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) macro
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| /prebuilts/ndk/9/platforms/android-19/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
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| cpu-features.h | 95 #ifndef cpu_has_llsc
96 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) macro
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| /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
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| cpu-features.h | 95 #ifndef cpu_has_llsc
96 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) macro
|
