| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| armSP_FFT_CToC_SC16_Radix8_fs_unsafe_s.S | 192 #define dT1 D1.S16
329 VQRDMULH dT1,dVr5,dT0[0] @// use dVi0 for dT1
334 VSUB dVr5,dT1,dVi5 @// a * V5
335 VADD dVi5,dT1,dVi5
340 VQRDMULH dT1,dVr7,dT0[0]
347 VADD dVr7,dT1,dVi7 @// b * V7
348 VSUB dVi7,dVi7,dT1
368 VQRDMULH dT1,dVr7,dT0[0]
373 VADD dVr7,dT1,dVi7 @// b * V
[all...] |
| armSP_FFT_CToC_SC32_Radix8_fs_unsafe_s.S | 188 #define dT1 D15.S32
320 VQRDMULH dT1,dVr5,dT0[0] @// use dVi0 for dT1
325 VSUB dVr5,dT1,dVi5 @// a * V5
326 VADD dVi5,dT1,dVi5
331 VQRDMULH dT1,dVr7,dT0[0]
338 VADD dVr7,dT1,dVi7 @// b * V7
339 VSUB dVi7,dVi7,dT1
359 VQRDMULH dT1,dVr7,dT0[0]
364 VADD dVr7,dT1,dVi7 @// b * V
[all...] |
| armSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.S | 174 #define dT1 D15.F32
308 VMUL dT1,dVr5,dT0[0] @// use dVi0 for dT1
314 VSUB dVr5,dT1,dVi5 @// a * V5
315 VADD dVi5,dT1,dVi5
320 VMUL dT1,dVr7,dT0[0]
327 VADD dVr7,dT1,dVi7 @// b * V7
328 VSUB dVi7,dVi7,dT1
352 VMUL dT1,dVr7,dT0[0]
357 VADD dVr7,dT1,dVi7 @// b * V
[all...] |
| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S | 102 #define dT1 D9.F32
219 VSUB dT1,dX0i,dX1i @// b-d
226 VMUL dT1, dT1, half[0]
245 VSUB dY1i,dX1r,dT1
252 VSUB dY0i,dT1,dX0r
|
| armSP_FFTInv_CCSToR_S32_preTwiddleRadix2_unsafe_s.S | 109 #define dT1 D9.S32
224 VHSUB dT1,dX0i,dX1i @// b-d
246 VHSUB dY1i,dX1r,dT1
249 VSUB dY1i,dX1r,dT1
263 VHSUB dY0i,dT1,dX0r
266 VSUB dY0i,dT1,dX0r
|
| omxSP_FFTFwd_RToCCS_F32_Sfs_s.S | 103 #define dT1 d7.f32
329 VSUB dT1,dX0i,dX1i @// b-d
332 VMUL dT1,dT1,half[0]
353 VADD dY1i,dT1,dX1r
364 VADD dY0i,dT1,dX0r
|
| omxSP_FFTFwd_RToCCS_S32_Sfs_s.S | 117 #define dT1 d7.s32
471 VSUB dT1,dX0i,dX1i @// b-d
473 VHADD dT1,dT1,dzero
494 VADD dY1i,dT1,dX1r
506 VADD dY0i,dT1,dX0r
|
| armSP_FFTInv_CCSToR_S16_preTwiddleRadix2_unsafe_s.S | 94 #define dT1 D9.S16
200 VHSUB dT1,dX0i,dX1i @ b-d
226 VHSUB dY1i,dX1r,dT1
229 VSUB dY1i,dX1r,dT1
234 VHSUB dY0i,dT1,dX0r
237 VSUB dY0i,dT1,dX0r
327 VHSUB dT1,dX0i,dX1i @ b-d
346 VHSUB dY1i,dX1r,dT1
349 VSUB dY1i,dX1r,dT1
360 VHSUB dY0i,dT1,dX0
[all...] |
| omxSP_FFTFwd_RToCCS_S16_Sfs_s.S | 104 #define dT1 d7.s16
484 VHSUB dT1,dX0i,dX1i @ (b-d)/2
499 VADD dY1i,dT1,dX1r
503 VADD dY0i,dT1,dX0r
577 VSUB dT1,dX0i,dX1i @ b-d
579 VHADD dT1,dT1,dzero
598 VADD dY1i,dT1,dX1r
608 VADD dY0i,dT1,dX0r
|
| omxSP_FFTInv_CCSToR_F32_Sfs_s.S | 111 #define dT1 D9.F32
|
| omxSP_FFTInv_CCSToR_S32_Sfs_s.S | 128 #define dT1 D9.S32
|
| omxSP_FFTInv_CCSToR_S16_Sfs_s.S | 101 #define dT1 D9.S32
|
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
| ComplexToRealFixup.S | 78 #define dT1 v7.2s
186 fsub dT1,dX0i,dX1i // b-d
189 fmul dT1,dT1,half[0]
215 fadd dY1i,dT1,dX1r
226 fadd dY0i,dT1,dX0r
|
| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_s.S | 93 #define dT1 v9.2s
201 fsub dT1,dX0i,dX1i // b-d
208 fmul dT1, dT1, half[0]
232 fsub dY1i,dX1r,dT1
239 fsub dY0i,dT1,dX0r
|
| armSP_FFT_CToC_FC32_Radix8_fs_s.S | 175 #define dT1 v15.2s
355 fmul dT1,dVr5,dT0[0] // use dVi0 for dT1
361 fsub dVr5,dT1,dVi5 // a * V5
362 fadd dVi5,dT1,dVi5
367 fmul dT1,dVr7,dT0[0]
377 fadd dVr7,dT1,dVi7 // b * V7
378 fsub dVi7,dVi7,dT1
402 fmul dT1,dVr7,dT0[0]
407 fadd dVr7,dT1,dVi7 // b * V
[all...] |
