/external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
armSP_FFT_CToC_SC16_Radix2_ps_unsafe_s.S | 75 #define dW1 D0.S16 130 VUZP dW1,dW2 134 VMULL qT0,dX1,dW1 136 VMULL qT1,dX3,dW1 140 VMULL qT0,dX1,dW1 142 VMULL qT1,dX3,dW1
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armSP_FFT_CToC_FC32_Radix4_unsafe_s.S | 79 #define dW1 D0.F32 134 VLD1 dW1,[pTwiddle] @//[wi | wr] 191 VMUL dZr1,dXr1,dW1[0] 192 VMUL dZi1,dXi1,dW1[0] 198 VMLA dZr1,dXi1,dW1[1] @// real part 199 VMLS dZi1,dXr1,dW1[1] @// imag part 213 VMUL dZr1,dXr1,dW1[0] 214 VMUL dZi1,dXi1,dW1[0] 220 VMLS dZr1,dXi1,dW1[1] @// real part 221 VMLA dZi1,dXr1,dW1[1] @// imag par [all...] |
armSP_FFT_CToC_SC16_Radix4_unsafe_s.S | 86 #define dW1 D0.S16 153 VLD1 dW1,[pTwiddle :64] @//[wi | wr] 188 VMULL qT0,dXr1,dW1[0] 189 VMLAL qT0,dXi1,dW1[1] @// real part 190 VMULL qT1,dXi1,dW1[0] 191 VMLSL qT1,dXr1,dW1[1] @// imag part 194 VMULL qT0,dXr1,dW1[0] 195 VMLSL qT0,dXi1,dW1[1] @// real part 196 VMULL qT1,dXi1,dW1[0] 197 VMLAL qT1,dXr1,dW1[1] @// imag par [all...] |
armSP_FFT_CToC_SC32_Radix4_unsafe_s.S | 88 #define dW1 D0.S32 144 VLD1 dW1,[pTwiddle] @//[wi | wr] 197 VMULL qT0,dXr1,dW1[0] 198 VMLAL qT0,dXi1,dW1[1] @// real part 199 VMULL qT1,dXi1,dW1[0] 200 VMLSL qT1,dXr1,dW1[1] @// imag part 203 VMULL qT0,dXr1,dW1[0] 204 VMLSL qT0,dXi1,dW1[1] @// real part 205 VMULL qT1,dXi1,dW1[0] 206 VMLAL qT1,dXr1,dW1[1] @// imag par [all...] |
armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S | 117 #define dW1 D7.F32
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armSP_FFTInv_CCSToR_S32_preTwiddleRadix2_unsafe_s.S | 124 #define dW1 D7.S32
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omxSP_FFTInv_CCSToR_F32_Sfs_s.S | 127 #define dW1 D7.F32
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omxSP_FFTFwd_RToCCS_F32_Sfs_s.S | 123 #define dW1 d5.f32
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omxSP_FFTInv_CCSToR_S32_Sfs_s.S | 144 #define dW1 D7.S32
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omxSP_FFTFwd_RToCCS_S32_Sfs_s.S | 137 #define dW1 d5.s32
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omxSP_FFTInv_CCSToR_S16_Sfs_s.S | 118 #define dW1 D7.S32
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armSP_FFTInv_CCSToR_S16_preTwiddleRadix2_unsafe_s.S | 109 #define dW1 D7.S16
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omxSP_FFTFwd_RToCCS_S16_Sfs_s.S | 139 #define dW1 d5.s16
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/external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
armSP_FFT_CToC_FC32_Radix4_s.S | 82 #define dW1 v0.2s 126 ld1 {dW1},[pTwiddle] //[wi | wr] 185 fmul dZr1,dXr1,dW1[0] 186 fmul dZi1,dXi1,dW1[0] 192 fmla dZr1,dXi1,dW1[1] // real part 193 fmls dZi1,dXr1,dW1[1] // imag part 207 fmul dZr1,dXr1,dW1[0] 208 fmul dZi1,dXi1,dW1[0] 214 fmls dZr1,dXi1,dW1[1] // real part 215 fmla dZi1,dXr1,dW1[1] // imag par [all...] |
armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_s.S | 108 #define dW1 v7.2s
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