/external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
armSP_FFTInv_CCSToR_S32_preTwiddleRadix2_unsafe_s.S | 100 #define dX0r D0.S32 205 VLD2 {dX0r,dX0i},[pSrc],step 220 VHSUB dT2,dX0r,dX1r @// a-c 223 VHADD dT0,dX0r,dX1r @// a+c 258 VRSHRN dX0r,qT2,#31 263 VHSUB dY0i,dT1,dX0r 266 VSUB dY0i,dT1,dX0r 290 VLD1 dX0r,[pSrc] 293 VSHR dX0r,dX0r,# [all...] |
armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S | 93 #define dX0r D0.F32 201 VLD2 {dX0r,dX0i},[pSrc],step 216 VSUB dT2,dX0r,dX1r @// a-c 218 VADD dT0,dX0r,dX1r @// a+c 234 VMUL dX0r,dW0r,dT2 240 VMLA dX0r,dW0i,dT3 252 VSUB dY0i,dT1,dX0r 277 VLD1 dX0r,[pSrc] 279 VST1 dX0r[0],[pOut1]! 280 VNEG dX0r,dX0 [all...] |
omxSP_FFTFwd_RToCCS_F32_Sfs_s.S | 98 #define dX0r d2.f32 269 VLD2 {dX0r[0],dX0i[0]},[pSrc]! 271 VMOV dX0r[1],zero 277 VADD dY0r,dX0r,dX0i @// F(0) = ((Z0.r+Z0.i) , 0) 279 VSUB dY0i,dX0r,dX0i @// F(N/2) = ((Z0.r-Z0.i) , 0) 308 VLD2 {dX0r,dX0i},[pSrc],step 326 VSUB dT2,dX0r,dX1r @// a-c 328 VADD dT0,dX0r,dX1r @// a+c 360 VMUL dX0r,qT2,half[0] 364 VADD dY0i,dT1,dX0r [all...] |
omxSP_FFTFwd_RToCCS_S32_Sfs_s.S | 112 #define dX0r d2.s32 412 VLD2 {dX0r[0],dX0i[0]},[pSrc]! 414 VMOV dX0r[1],zero 419 VADD dY0r,dX0r,dX0i @// F(0) = ((Z0.r+Z0.i) , 0) 421 VSUB dY0i,dX0r,dX0i @// F(N/2) = ((Z0.r-Z0.i) , 0) 449 VLD2 {dX0r,dX0i},[pSrc],step 467 VSUB dT2,dX0r,dX1r @// a-c 470 VADD dT0,dX0r,dX1r @// a+c 501 VRSHRN dX0r,qT2,#32 506 VADD dY0i,dT1,dX0r [all...] |
omxSP_FFTFwd_RToCCS_S16_Sfs_s.S | 94 #define dX0r d2.s16 426 VLD2 {dX0r[0],dX0i[0]},[pSrc]! 428 VMOV dX0r[1],zero 433 VADD dY0r,dX0r,dX0i @ F(0) = ((Z0.r+Z0.i) , 0) 435 VSUB dY0i,dX0r,dX0i @ F(N/2) = ((Z0.r-Z0.i) , 0) 459 VLD2 {dX0r,dX0i},[pSrc],step 468 VSUB dT2,dX0r,dX1r @ a-c 482 VHADD dT0,dX0r,dX1r @ (a+c)/2 498 VHSUB dX0r, d18s16, d19s16 503 VADD dY0i,dT1,dX0r [all...] |
armSP_FFTInv_CCSToR_S16_preTwiddleRadix2_unsafe_s.S | 79 #define dX0r D0.S16 185 VLD2 {dX0r,dX0i},[pSrc],step 192 VHSUB dT2,dX0r,dX1r @ a-c 199 VHADD dT0,dX0r,dX1r @ a+c 221 VRSHRN dX0r,qT2,#15 234 VHSUB dY0i,dT1,dX0r 237 VSUB dY0i,dT1,dX0r 306 VLD2 {dX0r[0],dX0i[0]},[pSrc]! 307 VLD2 {dX0r[1],dX0i[1]},[pSrc],step 323 VHSUB dT2,dX0r,dX1r @ a- [all...] |
omxSP_FFTInv_CCSToR_F32_Sfs_s.S | 102 #define dX0r D0.F32
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omxSP_FFTInv_CCSToR_S32_Sfs_s.S | 119 #define dX0r D0.S32
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omxSP_FFTInv_CCSToR_S16_Sfs_s.S | 92 #define dX0r D0.S32
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/external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
ComplexToRealFixup.S | 71 #define dX0r v2.2s 134 fadd dY0r,dX0r,dX0i // F(0) = ((Z0.r+Z0.i) , 0) 136 fsub dY0i,dX0r,dX0i // F(N/2) = ((Z0.r-Z0.i) , 0) 165 ld2 {dX0r,dX0i},[pSrc],step 183 fsub dT2,dX0r,dX1r // a-c 185 fadd dT0,dX0r,dX1r // a+c 222 fmul dX0r,qT2,half[0] 226 fadd dY0i,dT1,dX0r 251 ld1 {dX0r},[pSrc] 254 fneg dX0r,dX0 [all...] |
armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_s.S | 81 #define dX0r v0.2s 183 ld2 {dX0r,dX0i},[pSrc],step 198 fsub dT2,dX0r,dX1r // a-c 200 fadd dT0,dX0r,dX1r // a+c 221 fmul dX0r,dW0r,dT2 227 fmla dX0r,dW0i,dT3 239 fsub dY0i,dT1,dX0r 264 ld1 {dX0r},[pSrc] 267 fneg dX0r,dX0r [all...] |