| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_s.S | 85 #define dX1i v3.2s
185 ld2 {dX1r,dX1i},[pSrc], #16
194 rev64 dX1i,dX1i
199 fadd dT3,dX0i,dX1i // b+d
201 fsub dT1,dX0i,dX1i // b-d
220 fmul dX1i,dW1r,dT3
225 fmla dX1i,dW1i,dT2
231 fadd dY1r,dT0,dX1i // F(N/2 -1)
|
| ComplexToRealFixup.S | 76 #define dX1i v5.2s
167 ld2 {dX1r,dX1i},[pSrc], #16
178 rev64 dX1i,dX1i
186 fsub dT1,dX0i,dX1i // b-d
187 fadd dT3,dX0i,dX1i // b+d
212 fmul dX1i,qT1,half[0]
214 fsub dY1r,dT0,dX1i // F(N/2 -1)
|
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S | 96 #define dX1i D3.F32
203 VLD2 {dX1r,dX1i},[pSrc]!
212 VREV64 dX1i,dX1i
217 VADD dT3,dX0i,dX1i @// b+d
219 VSUB dT1,dX0i,dX1i @// b-d
233 VMUL dX1i,dW1r,dT3
238 VMLA dX1i,dW1i,dT2
244 VADD dY1r,dT0,dX1i @// F(N/2 -1)
|
| armSP_FFTInv_CCSToR_S32_preTwiddleRadix2_unsafe_s.S | 103 #define dX1i D3.S32
207 VLD2 {dX1r,dX1i},[pSrc]!
216 VREV64 dX1i,dX1i
221 VHADD dT3,dX0i,dX1i @// b+d
224 VHSUB dT1,dX0i,dX1i @// b-d
242 VRSHRN dX1i,qT1,#31
245 VHADD dY1r,dT0,dX1i @// F(N/2 -1)
248 VADD dY1r,dT0,dX1i @// F(N/2 -1)
|
| omxSP_FFTFwd_RToCCS_F32_Sfs_s.S | 101 #define dX1i d5.f32
310 VLD2 {dX1r,dX1i},[pSrc]!
321 VREV64 dX1i,dX1i
329 VSUB dT1,dX0i,dX1i @// b-d
330 VADD dT3,dX0i,dX1i @// b+d
350 VMUL dX1i,qT1,half[0]
352 VSUB dY1r,dT0,dX1i @// F(N/2 -1)
|
| omxSP_FFTFwd_RToCCS_S32_Sfs_s.S | 115 #define dX1i d5.s32
451 VLD2 {dX1r,dX1i},[pSrc]!
462 VREV64 dX1i,dX1i
469 VADD dT3,dX0i,dX1i @// b+d
471 VSUB dT1,dX0i,dX1i @// b-d
491 VRSHRN dX1i,qT1,#32
493 VSUB dY1r,dT0,dX1i @// F(N/2 -1)
|
| armSP_FFTInv_CCSToR_S16_preTwiddleRadix2_unsafe_s.S | 83 #define dX1i D3.S16
186 VLD2 {dX1r,dX1i},[pSrc]!
197 VHADD dT3,dX0i,dX1i @ b+d
200 VHSUB dT1,dX0i,dX1i @ b-d
220 VRSHRN dX1i,qT1,#15
225 VHADD dY1r,dT0,dX1i @ F(N/2 -1)
228 VADD dY1r,dT0,dX1i @ F(N/2 -1)
310 VLD2 {dX1r[0],dX1i[0]},[pSrc]!
311 VLD2 {dX1r[1],dX1i[1]},[pSrc]!
320 VREV32 dX1i,dX1
[all...] |
| omxSP_FFTFwd_RToCCS_S16_Sfs_s.S | 97 #define dX1i d5.s16
460 VLD2 {dX1r,dX1i},[pSrc],stepr
472 VADD dT3,dX0i,dX1i @ b+d
484 VHSUB dT1,dX0i,dX1i @ (b-d)/2
497 VHSUB dX1i, dY2, dY3
501 VSUB dY1r,dT0,dX1i @ F(N/2 -1)
560 VLD2 {dX1r[0],dX1i[0]},[pSrc]!
561 VLD2 {dX1r[1],dX1i[1]},[pSrc]!
570 VREV32 dX1i,dX1i
[all...] |
| omxSP_FFTInv_CCSToR_F32_Sfs_s.S | 105 #define dX1i D3.F32
|
| omxSP_FFTInv_CCSToR_S32_Sfs_s.S | 122 #define dX1i D3.S32
|
| omxSP_FFTInv_CCSToR_S16_Sfs_s.S | 95 #define dX1i D3.S32
|
