/external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
omxSP_FFTInv_CCSToR_S32S16_Sfs_s.S | 80 #define dY0 D2.S16 117 VQMOVN dY0,qX0 118 VST1 dY0[0],[pTmpDst] 125 VQMOVN dY0,qX0 133 VQMOVN dY0,qX0 134 VST1 dY0,[pTmpDst]!
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armSP_FFT_CToC_SC32_Radix2_fs_unsafe_s.S | 80 #define dY0 D2.S32 116 VHADD dY0,dX0,dX1 121 VADD dY0,dX0,dX1 127 VST1 dY0,[pDst],outPointStep
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armSP_FFT_CToC_FC32_Radix2_fs_unsafe_s.S | 72 #define dY0 D2.F32 106 VADD dY0,dX0,dX1 109 VST1 dY0,[pDst],outPointStep
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armSP_FFT_CToC_SC16_Radix2_fs_unsafe_s.S | 80 #define dY0 D2.S16 120 VHADD dY0,dX0,dX1 125 VADD dY0,dX0,dX1
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armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S | 91 #define dY0 D2.F32 162 VADD dY0,dX0,dX1 @// [b+d | a+c] 164 VMUL dY0, dY0, half[0] 167 @// dY0= [a-c | a+c] ;dY1= [b-d | b+d] 168 VZIP dY0,dY1 170 VSUB dX0,dY0,dY1 172 VADD dX1,dY0,dY1
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armSP_FFTInv_CCSToR_S32_preTwiddleRadix2_unsafe_s.S | 98 #define dY0 D2.S32 166 VHADD dY0,dX0,dX1 @// [b+d | a+c] 168 VZIP dY0,dY1 @// dY0= [a-c | a+c] ;dY1= [b-d | b+d] 171 VHSUB dX0,dY0,dY1 173 VHADD dX1,dY0,dY1 175 VSUB dX0,dY0,dY1 177 VADD dX1,dY0,dY1
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armSP_FFT_CToC_FC32_Radix2_unsafe_s.S | 77 #define dY0 D6.F32 149 VSUB dY0,dX0,qT0 154 VST2 {dY0,dY1},[pDst],outPointStep
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armSP_FFT_CToC_SC16_Radix2_ps_unsafe_s.S | 82 #define dY0 D6.S16 155 VHSUB dY0,dX0,dX1 162 VSUB dY0,dX0,dX1 171 VST1 dY0,[pDst],outPointStep @// point0: of set0,set1 of grp0
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armSP_FFT_CToC_SC16_Radix2_unsafe_s.S | 83 #define dY0 D6.S16 157 VHSUB dY0,dX0,dX2 163 VSUB dY0,dX0,dX2 170 VST2 {dY0,dY1},[pDst],outPointStep
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armSP_FFT_CToC_SC32_Radix2_unsafe_s.S | 85 #define dY0 D6.S32 158 VHSUB dY0,dX0,dX2 164 VSUB dY0,dX0,dX2 171 VST2 {dY0,dY1},[pDst],outPointStep
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armSP_FFTInv_CCSToR_S16_preTwiddleRadix2_unsafe_s.S | 77 #define dY0 D2.S16 151 VHADD dY0,dX0,dX1 @ [b+d | a+c] 153 VTRN dY0,dY1 @ dY0= [a-c | a+c] ;dY1= [b-d | b+d] 156 VHSUB dX0,dY0,dY1 158 VHADD dX1,dY0,dY1 160 VSUB dX0,dY0,dY1 162 VADD dX1,dY0,dY1 271 VHADD dY0,dX0,dX1 @ [b+d | a+c] 273 VTRN dY0,dY1 @ dY0= [a-c | a+c] ;dY1= [b-d | b+d] [all...] |
omxSP_FFTInv_CCSToR_F32_Sfs_s.S | 100 #define dY0 D2.F32
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omxSP_FFTFwd_RToCCS_F32_Sfs_s.S | 124 #define dY0 d10.f32
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omxSP_FFTInv_CCSToR_S32_Sfs_s.S | 117 #define dY0 D2.S32
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omxSP_FFTFwd_RToCCS_S16_Sfs_s.S | 140 #define dY0 d10.s16 486 VQDMULH dY0,dW1i,dT2 496 VRHADD dX1r, dY0, dY1
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omxSP_FFTFwd_RToCCS_S32_Sfs_s.S | 138 #define dY0 d10.s32
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omxSP_FFTInv_CCSToR_S16_Sfs_s.S | 90 #define dY0 D2.S32
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/external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
armSP_FFT_CToC_FC32_Radix2_fs_s.S | 72 #define dY0 v2.2s 108 fadd dY0,dX0,dX1 111 ST1 {dY0},[pDst],outPointStep
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armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_s.S | 78 #define dY0 v2.2s 141 fadd dY0,dX0,dX1 // [b+d | a+c] 143 fmul dY0, dY0, half[0] 146 // dY0= [a-c | a+c] ;dY1= [b-d | b+d] 147 // VZIP dY0,dY1 148 zip1 dZip,dY0,dY1 149 zip2 dY1,dY0,dY1 152 fsub dX0,dY0,dY1 154 fadd dX1,dY0,dY [all...] |
armSP_FFT_CToC_FC32_Radix2_s.S | 77 #define dY0 v6.2s 152 fsub dY0,dX0,qT0 157 st2 {dY0,dY1},[pDst],outPointStep
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