| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 20 dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 22 dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 22 dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 24 dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 24 dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 24 dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 59 dmfc1 $12,$f13
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 61 dmfc1 $12,$f13
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 61 dmfc1 $12,$f13
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 66 dmfc1 $12,$f13
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 67 dmfc1 $12,$f13
|
| /external/chromium_org/v8/test/cctest/ |
| test-assembler-mips64.cc | 374 __ dmfc1(a6, f5);
823 __ dmfc1(a7, f31);
[all...] |
| /external/chromium_org/v8/src/mips64/ |
| assembler-mips64.h | [all...] |
| assembler-mips64.cc | 2251 void Assembler::dmfc1(Register rt, FPURegister fs) { function in class:v8::Assembler
[all...] |
| macro-assembler-mips64.cc | [all...] |
