| /external/llvm/lib/Target/ARM/ |
| Thumb2RegisterInfo.cpp | 50 .addReg(DestReg, getDefRegState(true), SubIdx)
|
| ARMLoadStoreOptimizer.cpp | 525 MIB.addReg(Base, getDefRegState(true))
542 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
[all...] |
| ARMBaseInstrInfo.h | 339 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
|
| MLxExpansionPass.cpp | 301 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
|
| ARMBaseRegisterInfo.cpp | 412 .addReg(DestReg, getDefRegState(true), SubIdx)
|
| Thumb1FrameLowering.cpp | 478 MIB.addReg(Reg, getDefRegState(true));
|
| Thumb1RegisterInfo.cpp | 77 .addReg(DestReg, getDefRegState(true), SubIdx)
|
| ARMFrameLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 191 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 388 inline unsigned getDefRegState(bool B) {
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 752 MIB.addReg(Reg2, getDefRegState(true))
753 .addReg(Reg1, getDefRegState(true))
[all...] |
| AArch64InstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 362 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 178 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
[all...] |
| X86InstrInfo.cpp | [all...] |
