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    Searched refs:getRegClassFor (Results 1 - 22 of 22) sorted by null

  /external/llvm/lib/CodeGen/SelectionDAG/
ResourcePriorityQueue.cpp 100 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
138 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
338 && TLI->getRegClassFor(VT)
339 && TLI->getRegClassFor(VT)->getID() == RCId)
349 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT)
350 && TLI->getRegClassFor(VT)->getID() == RCId)
491 const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
502 const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
InstrEmitter.cpp 108 UseRC = TLI->getRegClassFor(VT);
166 DstRC = TLI->getRegClassFor(VT);
228 TLI->getRegClassFor(Node->getSimpleValueType(i));
289 TLI->getRegClassFor(Op.getSimpleValueType());
452 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
487 TLI->getRegClassFor(Node->getSimpleValueType(0));
542 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0));
    [all...]
FastISel.cpp 235 Reg = createResultReg(TLI.getRegClassFor(VT));
    [all...]
FunctionLoweringInfo.cpp 249 createVirtualRegister(TM.getTargetLowering()->getRegClassFor(VT));
SelectionDAGISel.cpp     [all...]
SelectionDAGBuilder.cpp     [all...]
DAGCombiner.cpp     [all...]
  /external/llvm/lib/Target/ARM/
ARMFastISel.cpp 448 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
458 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
484 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
500 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
537 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
549 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
650 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
664 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
715 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
    [all...]
ARMISelLowering.h 350 /// getRegClassFor - Return the register class that should be used for the
352 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
ARMISelLowering.cpp     [all...]
  /external/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 217 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
235 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
554 RC = TLI.getRegClassFor(VT);
559 RC = TLI.getRegClassFor(VT);
    [all...]
  /external/llvm/lib/Target/X86/
X86FastISel.cpp     [all...]
X86ISelLowering.cpp     [all...]
  /external/llvm/lib/Target/Mips/
MipsISelLowering.cpp     [all...]
MipsSEISelDAGToDAG.cpp 860 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
  /external/llvm/lib/Target/PowerPC/
PPCFastISel.cpp     [all...]
PPCISelLowering.cpp     [all...]
  /external/llvm/include/llvm/Target/
TargetLowering.h 314 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp     [all...]
  /external/llvm/lib/Target/R600/
SIISelLowering.cpp     [all...]
  /external/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 567 getRegClassFor(VA.getLocVT()));
    [all...]
  /external/llvm/lib/CodeGen/
MachineScheduler.cpp     [all...]

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