| /external/llvm/test/MC/ARM/ |
| target-expressions.s | 19 movt r0, :upper16:function
22 movt r1, #:upper16:function
25 movt r2, :upper16:deadbeat
28 movt r3, #:upper16:deadbeat
31 movt r4, :upper16:0xD1510D6E
34 movt r5, #:upper16:0xD1510D6E
37 movt r0, :upper16:external
40 movt r1, #:upper16:external
43 movt r2, #:upper16:(16 + 16)
46 movt r3, :upper16:(16 + 16
[all...] |
| thumb2be-movt-encoding.s | 4 movt r9, :upper16:(_bar) label
5 @ CHECK-LE: movt r9, :upper16:_bar @ encoding: [0xc0'A',0xf2'A',0b0000AAAA,0x09]
7 @ CHECK-BE: movt r9, :upper16:_bar @ encoding: [0xf2,0b1100AAAA,0x09'A',A]
|
| hilo-16bit-relocations.s | 6 movt r0, :upper16:(L_foo$non_lazy_ptr - (L1 + 8))
10 @ CHECK: movt r0, :upper16:(L_foo$non_lazy_ptr-(L1+8))
|
| 2010-11-30-reloc-movt.s | 14 .file "/home/espindola/llvm/llvm/test/CodeGen/ARM/2010-11-30-reloc-movt.ll"
23 movt r0, :upper16:a
|
| big-endian-thumb2-fixup.s | 17 movt r0, :upper16:GOT-(movt_label)
|
| arm_fixups.s | 14 movt r9, :upper16:(_foo)
24 @ CHECK: movt r9, :upper16:_foo @ encoding: [A,0x90'A',0b0100AAAA,0xe3]
26 @ CHECK-BE: movt r9, :upper16:_foo @ encoding: [0xe3,0b0100AAAA,0x90'A',A]
|
| elf-movt.s | 12 movt r0, :upper16:GOT-(.LPC0_2+8)
15 @ ASM-NEXT: movt r0, :upper16:(GOT-(.LPC0_2+8))
|
| big-endian-arm-fixup.s | 81 movt r0, :upper16:GOT-(movt_label)
|
| coff-relocations.s | 37 movt r0, :upper16:target
42 @ CHECK-ENCODING-NEXT: movt r0, #0
|
| /external/llvm/test/MC/MachO/ARM/ |
| thumb2-movt-fixup.s | 4 movt r3, :upper16:(_wilma-(LPC0_0+4))
|
| thumb2-movw-fixup.s | 11 movt r2, :upper16:L1
13 movt r12, :upper16:L2
|
| static-movt-relocs.s | 6 movt r0, :upper16:(bar + 16)
|
| /external/valgrind/main/none/tests/mips32/ |
| MoveIns.stdout.exp | 226 MOVT
227 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
228 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
229 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1
230 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0
231 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
232 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0
233 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1
234 movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0
235 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc:
[all...] |
| /external/llvm/test/MC/Mips/ |
| micromips-movcond-instructions.s | 14 # CHECK-EL: movt $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x09]
21 # CHECK-EB: movt $9, $6, $fcc0 # encoding: [0x55,0x26,0x09,0x7b]
25 movt $9, $6, $fcc0
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips4.s | 21 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
22 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
23 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips5.s | 22 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
23 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
24 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
26 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/valgrind/main/coregrind/m_dispatch/ |
| dispatch-arm-linux.S | 129 4 = movt r12, hi16(disp_cp_chain_me_to_slowEP)
144 4 = movt r12, hi16(disp_cp_chain_me_to_fastEP)
157 movt r1, #:upper16:vgPlain_stats__n_xindirs_32
168 movt r4, #:upper16:VG_(tt_fast) // r4 = &VG_(tt_fast)
182 movt r1, #:upper16:vgPlain_stats__n_xindir_misses_32
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips32.s | 18 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
19 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
20 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/ARM/Windows/ |
| mov32t-range.s | 19 movt r0, :upper16:.Lerange
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32.s | 31 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
32 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
33 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
34 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
35 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips32r2.s | 38 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
39 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
40 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
41 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
42 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips4.s | 60 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
61 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
62 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
63 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
64 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips5.s | 59 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
60 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
61 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
62 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
63 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips64.s | 32 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
33 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
34 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/armv7/ |
| omxSP_FFTInv_CToC_FC32_Sfs_s.S | 153 movt round, #0x3f80 @// round = 1.0
|
