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Searched
refs:pnw_cmdbuf_insert_reg_write
(Results
1 - 2
of
2
) sorted by null
/hardware/intel/img/psb_video/src/
pnw_hostcode.c
202
pnw_cmdbuf_insert_reg_write
(MVEARegBase[i32Core], MVEA_CR_SPE_ZERO_THRESH, SPE_ZERO_THRESHOLD);
218
pnw_cmdbuf_insert_reg_write
(MVEARegBase[i32Core], MVEA_CR_IPE_LAMBDA_TABLE, ui32RegVal);
231
pnw_cmdbuf_insert_reg_write
(MVEARegBase[i32Core], MVEA_CR_IPE_MV_BIAS_TABLE, uIPESkipVecBias);
232
pnw_cmdbuf_insert_reg_write
(MVEARegBase[i32Core], MVEA_CR_SPE_PRED_VECTOR_BIAS_TABLE, uIPESkipVecBias);
233
pnw_cmdbuf_insert_reg_write
(MVEARegBase[i32Core], MVEA_CR_SPE_INTRA16_BIAS_TABLE, iIntra16Bias);
234
pnw_cmdbuf_insert_reg_write
(MVEARegBase[i32Core], MVEA_CR_SPE_INTER_BIAS_TABLE, iInterMBBias);
259
pnw_cmdbuf_insert_reg_write
(MVEARegBase[i32Core], MVEA_CR_SPE_ZERO_THRESH, SPE_ZERO_THRESHOLD);
276
pnw_cmdbuf_insert_reg_write
(MVEARegBase[i32Core], MVEA_CR_IPE_LAMBDA_TABLE, ui32RegVal);
289
pnw_cmdbuf_insert_reg_write
(MVEARegBase[i32Core], MVEA_CR_IPE_MV_BIAS_TABLE, uIPESkipVecBias);
290
pnw_cmdbuf_insert_reg_write
(MVEARegBase[i32Core], MVEA_CR_SPE_PRED_VECTOR_BIAS_TABLE, uIPESkipVecBias)
[
all
...]
pnw_cmdbuf.h
187
#define
pnw_cmdbuf_insert_reg_write
(base, offset, value) \
macro
Completed in 4982 milliseconds