/external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
armSP_FFT_CToC_FC32_Radix2_ls_s.S | 74 #define qT0 v10.2s 110 fmul qT0,dWr,dXr1 111 fmla qT0,dWi,dXi1 // real part 117 fmul qT0,dWr,dXr1 118 fmls qT0,dWi,dXi1 // real part 124 fsub dYr0,dXr0,qT0 126 fadd dYr1,dXr0,qT0
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armSP_FFT_CToC_FC32_Radix2_s.S | 81 #define qT0 v10.2s 138 fmul qT0,dX2,dW[0] 139 fmla qT0,dX3,dW[1] // real part 145 fmul qT0,dX2,dW[0] 146 fmls qT0,dX3,dW[1] // real part 152 fsub dY0,dX0,qT0 154 fadd dY2,dX0,qT0
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ComplexToRealFixup.S | 81 #define qT0 v10.2s 199 fmul qT0,dW1r,dT2 204 fmla qT0,dW1i,dT3 211 fmul dX1r,qT0,half[0]
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armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_s.S | 96 #define qT0 v12.2s
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/external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
armSP_FFT_CToC_FC32_Radix2_ls_unsafe_s.S | 73 #define qT0 d10.f32 106 VMUL qT0,dWr,dXr1 107 VMLA qT0,dWi,dXi1 @// real part 113 VMUL qT0,dWr,dXr1 114 VMLS qT0,dWi,dXi1 @// real part 120 VSUB dYr0,dXr0,qT0 122 VADD dYr1,dXr0,qT0
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armSP_FFT_CToC_FC32_Radix2_unsafe_s.S | 81 #define qT0 D10.F32 135 VMUL qT0,dX2,dW[0] 136 VMLA qT0,dX3,dW[1] @// real part 142 VMUL qT0,dX2,dW[0] 143 VMLS qT0,dX3,dW[1] @// real part 149 VSUB dY0,dX0,qT0 151 VADD dY2,dX0,qT0
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armSP_FFT_CToC_SC32_Radix2_ls_unsafe_s.S | 82 #define qT0 q5.s64 109 VMULL qT0,dWr,dXr1 110 VMLAL qT0,dWi,dXi1 @// real part 116 VMULL qT0,dWr,dXr1 117 VMLSL qT0,dWi,dXi1 @// real part 123 VRSHRN dXr1,qT0,#31
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armSP_FFT_CToC_SC16_Radix2_ls_unsafe_s.S | 90 #define qT0 Q5.S32 127 VMULL qT0,dXr1,dWr 128 VMLAL qT0,dXi1,dWi @// real part 133 VMULL qT0,dXr1,dWr 134 VMLSL qT0,dXi1,dWi @// real part 140 VRSHRN dXr1,qT0,#15
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armSP_FFT_CToC_SC16_Radix2_ps_unsafe_s.S | 86 #define qT0 Q5.S32 134 VMULL qT0,dX1,dW1 135 VMLAL qT0,dX3,dW2 @// real part 140 VMULL qT0,dX1,dW1 141 VMLSL qT0,dX3,dW2 @// real part 147 VRSHRN dX1,qT0,#15
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armSP_FFT_CToC_SC16_Radix2_unsafe_s.S | 87 #define qT0 Q3.S32 139 VMULL qT0,dX2,dW[0] 140 VMLAL qT0,dX3,dW[1] @// real part 146 VMULL qT0,dX2,dW[0] 147 VMLSL qT0,dX3,dW[1] @// real part 153 VRSHRN dX2,qT0,#15
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armSP_FFT_CToC_SC32_Radix2_unsafe_s.S | 89 #define qT0 Q3.S64 140 VMULL qT0,dX2,dW[0] 141 VMLAL qT0,dX3,dW[1] @// real part 147 VMULL qT0,dX2,dW[0] 148 VMLSL qT0,dX3,dW[1] @// real part 154 VRSHRN dX2,qT0,#31
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armSP_FFT_CToC_SC16_Radix4_ls_unsafe_s.S | 141 #define qT0 Q9.S32 216 VMULL qT0,dXr1,dW1r 217 VMLAL qT0,dXi1,dW1i @// real part 222 VMULL qT0,dXr1,dW1r 223 VMLSL qT0,dXi1,dW1i @// real part 246 VRSHRN dZr1,qT0,#15 252 VMULL qT0,dXr3,dW3r 253 VMLAL qT0,dXi3,dW3i @// real part 258 VMULL qT0,dXr3,dW3r 259 VMLSL qT0,dXi3,dW3i @// real par [all...] |
armSP_FFT_CToC_SC16_Radix4_unsafe_s.S | 106 #define qT0 Q8.S32 188 VMULL qT0,dXr1,dW1[0] 189 VMLAL qT0,dXi1,dW1[1] @// real part 194 VMULL qT0,dXr1,dW1[0] 195 VMLSL qT0,dXi1,dW1[1] @// real part 217 VRSHRN dZr1,qT0,#15 224 VMULL qT0,dXr3,dW3[0] 225 VMLAL qT0,dXi3,dW3[1] @// real part 230 VMULL qT0,dXr3,dW3[0] 231 VMLSL qT0,dXi3,dW3[1] @// real par [all...] |
armSP_FFT_CToC_SC32_Radix4_unsafe_s.S | 108 #define qT0 Q8.S64 197 VMULL qT0,dXr1,dW1[0] 198 VMLAL qT0,dXi1,dW1[1] @// real part 203 VMULL qT0,dXr1,dW1[0] 204 VMLSL qT0,dXi1,dW1[1] @// real part 226 VRSHRN dZr1,qT0,#31 232 VMULL qT0,dXr3,dW3[0] 233 VMLAL qT0,dXi3,dW3[1] @// real part 238 VMULL qT0,dXr3,dW3[0] 239 VMLSL qT0,dXi3,dW3[1] @// real par [all...] |
armSP_FFTInv_CCSToR_S32_preTwiddleRadix2_unsafe_s.S | 112 #define qT0 Q6.S64 230 VMULL qT0,dW1r,dT2 231 VMLSL qT0,dW1i,dT3 241 VRSHRN dX1r,qT0,#31
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armSP_FFT_CToC_SC32_Radix4_ls_unsafe_s.S | 111 #define qT0 Q7.S64 198 VMULL qT0,dW1r,dXr1 199 VMLAL qT0,dW1i,dXi1 @// real part 205 VMULL qT0,dW1r,dXr1 206 VMLSL qT0,dW1i,dXi1 @// real part 232 VRSHRN dZr1,qT0,#31
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omxSP_FFTFwd_RToCCS_F32_Sfs_s.S | 106 #define qT0 d10.f32 337 VMUL qT0,dW1r,dT2 342 VMLA qT0,dW1i,dT3 349 VMUL dX1r,qT0,half[0]
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omxSP_FFTFwd_RToCCS_S32_Sfs_s.S | 120 #define qT0 q5.s64 479 VMULL qT0,dW1r,dT2 480 VMLAL qT0,dW1i,dT3 490 VRSHRN dX1r,qT0,#32
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armSP_FFTInv_CCSToR_S16_preTwiddleRadix2_unsafe_s.S | 97 #define qT0 Q6.S32 210 VMULL qT0,dW1i,dT2 211 VMLSL qT0,dW1r,dT3 219 VRSHRN dX1r,qT0,#15 332 VMULL qT0,dW1r,dT2 333 VMLSL qT0,dW1i,dT3 341 VRSHRN dX1r,qT0,#15
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armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S | 105 #define qT0 D12.F32
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omxSP_FFTFwd_RToCCS_S16_Sfs_s.S | 107 #define qT0 q5.s32 584 VMULL qT0,dW1r,dT2 585 VMLAL qT0,dW1i,dT3 594 VRSHRN dX1r,qT0,#16
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omxSP_FFTInv_CCSToR_F32_Sfs_s.S | 114 #define qT0 d12.F32
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armSP_FFT_CToC_FC32_Radix4_ls_unsafe_s.S | 103 #define qT0 d14.f32
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armSP_FFT_CToC_FC32_Radix4_unsafe_s.S | 99 #define qT0 d16.f32
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omxSP_FFTInv_CCSToR_S32_Sfs_s.S | 131 #define qT0 Q6.S64
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