| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
| armSP_FFT_CToC_FC32_Radix2_ls_s.S | 75 #define qT1 v12.2s
112 fmul qT1,dWr,dXi1
113 fmls qT1,dWi,dXr1 // imag part
119 fmul qT1,dWr,dXi1
120 fmla qT1,dWi,dXr1 // imag part
125 fsub dYi0,dXi0,qT1
127 fadd dYi1,dXi0,qT1
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| armSP_FFT_CToC_FC32_Radix2_s.S | 82 #define qT1 v11.2s
140 fmul qT1,dX3,dW[0]
141 fmls qT1,dX2,dW[1] // imag part
147 fmul qT1,dX3,dW[0]
148 fmla qT1,dX2,dW[1] // imag part
153 fsub dY1,dX1,qT1
155 fadd dY3,dX1,qT1
|
| ComplexToRealFixup.S | 82 #define qT1 v12.2s
200 fmul qT1,dW1r,dT3
205 fmls qT1,dW1i,dT2
212 fmul dX1i,qT1,half[0]
|
| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_s.S | 97 #define qT1 v14.2s
|
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| armSP_FFT_CToC_FC32_Radix2_ls_unsafe_s.S | 74 #define qT1 d12.f32
108 VMUL qT1,dWr,dXi1
109 VMLS qT1,dWi,dXr1 @// imag part
115 VMUL qT1,dWr,dXi1
116 VMLA qT1,dWi,dXr1 @// imag part
121 VSUB dYi0,dXi0,qT1
123 VADD dYi1,dXi0,qT1
|
| armSP_FFT_CToC_FC32_Radix2_unsafe_s.S | 82 #define qT1 D11.F32
137 VMUL qT1,dX3,dW[0]
138 VMLS qT1,dX2,dW[1] @// imag part
144 VMUL qT1,dX3,dW[0]
145 VMLA qT1,dX2,dW[1] @// imag part
150 VSUB dY1,dX1,qT1
152 VADD dY3,dX1,qT1
|
| armSP_FFT_CToC_SC32_Radix2_ls_unsafe_s.S | 83 #define qT1 q6.s64
111 VMULL qT1,dWr,dXi1
112 VMLSL qT1,dWi,dXr1 @// imag part
118 VMULL qT1,dWr,dXi1
119 VMLAL qT1,dWi,dXr1 @// imag part
124 VRSHRN dXi1,qT1,#31
|
| armSP_FFT_CToC_SC16_Radix2_ls_unsafe_s.S | 91 #define qT1 Q6.S32
129 VMULL qT1,dXi1,dWr
130 VMLSL qT1,dXr1,dWi @// imag part
135 VMULL qT1,dXi1,dWr
136 VMLAL qT1,dXr1,dWi @// imag part
141 VRSHRN dXi1,qT1,#15
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| armSP_FFT_CToC_SC16_Radix2_ps_unsafe_s.S | 87 #define qT1 Q6.S32
136 VMULL qT1,dX3,dW1
137 VMLSL qT1,dX1,dW2 @// imag part
142 VMULL qT1,dX3,dW1
143 VMLAL qT1,dX1,dW2 @// imag part
148 VRSHRN dX3,qT1,#15
|
| armSP_FFT_CToC_SC16_Radix2_unsafe_s.S | 88 #define qT1 Q4.S32
141 VMULL qT1,dX3,dW[0]
142 VMLSL qT1,dX2,dW[1] @// imag part
148 VMULL qT1,dX3,dW[0]
149 VMLAL qT1,dX2,dW[1] @// imag part
154 VRSHRN dX3,qT1,#15
|
| armSP_FFT_CToC_SC32_Radix2_unsafe_s.S | 90 #define qT1 Q4.S64
142 VMULL qT1,dX3,dW[0]
143 VMLSL qT1,dX2,dW[1] @// imag part
149 VMULL qT1,dX3,dW[0]
150 VMLAL qT1,dX2,dW[1] @// imag part
155 VRSHRN dX3,qT1,#31
|
| armSP_FFT_CToC_SC16_Radix4_ls_unsafe_s.S | 142 #define qT1 Q10.S32
218 VMULL qT1,dXi1,dW1r
219 VMLSL qT1,dXr1,dW1i @// imag part
224 VMULL qT1,dXi1,dW1r
225 VMLAL qT1,dXr1,dW1i @// imag part
247 VRSHRN dZi1,qT1,#15
254 VMULL qT1,dXi3,dW3r
255 VMLSL qT1,dXr3,dW3i @// imag part
260 VMULL qT1,dXi3,dW3r
261 VMLAL qT1,dXr3,dW3i @// imag par
[all...] |
| armSP_FFT_CToC_SC16_Radix4_unsafe_s.S | 107 #define qT1 Q9.S32
190 VMULL qT1,dXi1,dW1[0]
191 VMLSL qT1,dXr1,dW1[1] @// imag part
196 VMULL qT1,dXi1,dW1[0]
197 VMLAL qT1,dXr1,dW1[1] @// imag part
218 VRSHRN dZi1,qT1,#15
226 VMULL qT1,dXi3,dW3[0]
227 VMLSL qT1,dXr3,dW3[1] @// imag part
232 VMULL qT1,dXi3,dW3[0]
233 VMLAL qT1,dXr3,dW3[1] @// imag par
[all...] |
| armSP_FFT_CToC_SC32_Radix4_unsafe_s.S | 109 #define qT1 Q9.S64
199 VMULL qT1,dXi1,dW1[0]
200 VMLSL qT1,dXr1,dW1[1] @// imag part
205 VMULL qT1,dXi1,dW1[0]
206 VMLAL qT1,dXr1,dW1[1] @// imag part
227 VRSHRN dZi1,qT1,#31
234 VMULL qT1,dXi3,dW3[0]
235 VMLSL qT1,dXr3,dW3[1] @// imag part
240 VMULL qT1,dXi3,dW3[0]
241 VMLAL qT1,dXr3,dW3[1] @// imag par
[all...] |
| armSP_FFTInv_CCSToR_S32_preTwiddleRadix2_unsafe_s.S | 113 #define qT1 Q7.S64
232 VMULL qT1,dW1r,dT3
233 VMLAL qT1,dW1i,dT2
242 VRSHRN dX1i,qT1,#31
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| armSP_FFT_CToC_SC32_Radix4_ls_unsafe_s.S | 112 #define qT1 Q8.S64
200 VMULL qT1,dW1r,dXi1
201 VMLSL qT1,dW1i,dXr1 @// imag part
207 VMULL qT1,dW1r,dXi1
208 VMLAL qT1,dW1i,dXr1 @// imag part
234 VRSHRN dZi1,qT1,#31
|
| omxSP_FFTFwd_RToCCS_F32_Sfs_s.S | 107 #define qT1 d12.f32
338 VMUL qT1,dW1r,dT3
343 VMLS qT1,dW1i,dT2
350 VMUL dX1i,qT1,half[0]
|
| omxSP_FFTFwd_RToCCS_S32_Sfs_s.S | 121 #define qT1 q6.s64
481 VMULL qT1,dW1r,dT3
482 VMLSL qT1,dW1i,dT2
491 VRSHRN dX1i,qT1,#32
|
| armSP_FFTInv_CCSToR_S16_preTwiddleRadix2_unsafe_s.S | 98 #define qT1 Q7.S32
212 VMULL qT1,dW1i,dT3
213 VMLAL qT1,dW1r,dT2
220 VRSHRN dX1i,qT1,#15
334 VMULL qT1,dW1r,dT3
335 VMLAL qT1,dW1i,dT2
342 VRSHRN dX1i,qT1,#15
|
| armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S | 106 #define qT1 D14.F32
|
| omxSP_FFTFwd_RToCCS_S16_Sfs_s.S | 108 #define qT1 q6.s32
586 VMULL qT1,dW1r,dT3
587 VMLSL qT1,dW1i,dT2
595 VRSHRN dX1i,qT1,#16
|
| omxSP_FFTInv_CCSToR_F32_Sfs_s.S | 115 #define qT1 d14.F32
|
| armSP_FFT_CToC_FC32_Radix4_ls_unsafe_s.S | 104 #define qT1 d16.F32
|
| armSP_FFT_CToC_FC32_Radix4_unsafe_s.S | 100 #define qT1 d18.f32
|
| omxSP_FFTInv_CCSToR_S32_Sfs_s.S | 132 #define qT1 Q7.S64
|
