| /external/fio/engines/ |
| rdma.c | 121 struct rdmaio_data *rd = td->io_ops->data; local
123 if (wc->byte_len != sizeof(rd->recv_buf)) {
129 if ((rd->rdma_protocol == FIO_RDMA_MEM_WRITE) ||
130 (rd->rdma_protocol == FIO_RDMA_MEM_READ)) {
134 rd->rmt_nr = ntohl(rd->recv_buf.nr);
136 for (i = 0; i < rd->rmt_nr; i++) {
137 rd->rmt_us[i].buf = ntohll(rd->recv_buf.rmt_us[i].buf);
138 rd->rmt_us[i].rkey = ntohl(rd->recv_buf.rmt_us[i].rkey)
153 struct rdmaio_data *rd = td->io_ops->data; local
168 struct rdmaio_data *rd = td->io_ops->data; local
275 struct rdmaio_data *rd = td->io_ops->data; local
312 struct rdmaio_data *rd = td->io_ops->data; local
392 struct rdmaio_data *rd = td->io_ops->data; local
436 struct rdmaio_data *rd = td->io_ops->data; local
468 struct rdmaio_data *rd = td->io_ops->data; local
511 struct rdmaio_data *rd = td->io_ops->data; local
529 struct rdmaio_data *rd = td->io_ops->data; local
591 struct rdmaio_data *rd = td->io_ops->data; local
654 struct rdmaio_data *rd = td->io_ops->data; local
690 struct rdmaio_data *rd = td->io_ops->data; local
708 struct rdmaio_data *rd = td->io_ops->data; local
731 struct rdmaio_data *rd = td->io_ops->data; local
763 struct rdmaio_data *rd = td->io_ops->data; local
812 struct rdmaio_data *rd = td->io_ops->data; local
855 struct rdmaio_data *rd = td->io_ops->data; local
911 struct rdmaio_data *rd = td->io_ops->data; local
975 struct rdmaio_data *rd = td->io_ops->data; local
1051 struct rdmaio_data *rd = td->io_ops->data; local
1191 struct rdmaio_data *rd = td->io_ops->data; local
1199 struct rdmaio_data *rd; local
[all...] |
| /external/valgrind/main/none/tests/mips64/ |
| cvm_ins.stdout.exp | [all...] |
| /external/clang/test/CXX/temp/temp.param/ |
| p7.cpp | 9 template<double& rd> class Z; //OK
|
| /external/chromium_org/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 46 void MacroAssembler::And(const Register& rd,
50 DCHECK(!rd.IsZero());
51 LogicalMacro(rd, rn, operand, AND);
55 void MacroAssembler::Ands(const Register& rd,
59 DCHECK(!rd.IsZero());
60 LogicalMacro(rd, rn, operand, ANDS);
71 void MacroAssembler::Bic(const Register& rd,
75 DCHECK(!rd.IsZero());
76 LogicalMacro(rd, rn, operand, BIC);
80 void MacroAssembler::Bics(const Register& rd,
[all...] |
| assembler-arm64.h | [all...] |
| delayed-masm-arm64-inl.h | 23 void DelayedMasm::Mov(const Register& rd,
27 DCHECK(!IsScratchRegister(rd) || scratch_register_acquired_);
28 __ Mov(rd, operand, discard_mode);
|
| assembler-arm64.cc | 522 // Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0.
538 // Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0.
3128 Register rd = Register::XRegFromCode(rd_code); local
[all...] |
| /external/vixl/src/a64/ |
| macro-assembler-a64.h | 99 void And(const Register& rd,
102 void Ands(const Register& rd,
105 void Bic(const Register& rd,
108 void Bics(const Register& rd,
111 void Orr(const Register& rd,
114 void Orn(const Register& rd,
117 void Eor(const Register& rd,
120 void Eon(const Register& rd,
124 void LogicalMacro(const Register& rd,
130 void Add(const Register& rd,
[all...] |
| assembler-a64.cc | 533 void Assembler::adr(const Register& rd, int imm21) {
534 VIXL_ASSERT(rd.Is64Bits());
535 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd));
539 void Assembler::adr(const Register& rd, Label* label) {
540 adr(rd, UpdateAndGetByteOffsetTo(label));
544 void Assembler::add(const Register& rd,
547 AddSub(rd, rn, operand, LeaveFlags, ADD);
551 void Assembler::adds(const Register& rd,
554 AddSub(rd, rn, operand, SetFlags, ADD)
[all...] |
| assembler-a64.h | 731 void adr(const Register& rd, Label* label);
734 void adr(const Register& rd, int imm21);
738 void add(const Register& rd,
743 void adds(const Register& rd,
751 void sub(const Register& rd,
756 void subs(const Register& rd,
764 void neg(const Register& rd,
768 void negs(const Register& rd,
772 void adc(const Register& rd,
777 void adcs(const Register& rd,
[all...] |
| macro-assembler-a64.cc | 49 void MacroAssembler::And(const Register& rd,
53 LogicalMacro(rd, rn, operand, AND);
57 void MacroAssembler::Ands(const Register& rd,
61 LogicalMacro(rd, rn, operand, ANDS);
72 void MacroAssembler::Bic(const Register& rd,
76 LogicalMacro(rd, rn, operand, BIC);
80 void MacroAssembler::Bics(const Register& rd,
84 LogicalMacro(rd, rn, operand, BICS);
88 void MacroAssembler::Orr(const Register& rd,
92 LogicalMacro(rd, rn, operand, ORR)
[all...] |
| /external/valgrind/main/none/tests/arm/ |
| v6intARM.stdout.exp | 2 mov r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
3 cpy r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
4 mov r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
5 mov r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 0, cpsr 0x00000000
6 movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
7 movs r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x40000000 Z
8 movs r0, r1 :: rd 0x80000000 rm 0x80000000, carryin 0, cpsr 0x80000000 N
9 movs r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x40000000 Z
10 movs r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 0, cpsr 0x00000000
11 movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000 C
[all...] |
| v6media.stdout.exp | 2 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3 mul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
4 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
5 mul r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
6 mul r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
7 mul r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
9 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
10 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
11 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
12 mla r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=00 (…)
[all...] |
| /external/chromium_org/third_party/icu/source/test/cintltst/ |
| uregiontest.c | 362 const KnownRegion * rd; local
363 for (rd = knownRegions; rd->code != NULL ; rd++ ) {
365 const URegion *r = uregion_getRegionFromCode(rd->code, &status);
368 int32_t e = rd->numeric;
372 if (uregion_getType(r) != rd->type) {
373 log_err("ERROR: Expected region %s to be of type %d. Got: %d\n", uregion_getRegionCode(r), rd->type, uregion_getType(r) );
383 log_data_err("ERROR: Known region %s was not recognized.\n", rd->code);
389 const KnownRegion * rd; local
418 const KnownRegion * rd; local
447 const KnownRegion * rd; local
471 const KnownRegion * rd; local
548 const KnownRegion * rd; local
[all...] |
| /external/icu/icu4c/source/test/cintltst/ |
| uregiontest.c | 362 const KnownRegion * rd; local
363 for (rd = knownRegions; rd->code != NULL ; rd++ ) {
365 const URegion *r = uregion_getRegionFromCode(rd->code, &status);
368 int32_t e = rd->numeric;
372 if (uregion_getType(r) != rd->type) {
373 log_err("ERROR: Expected region %s to be of type %d. Got: %d\n", uregion_getRegionCode(r), rd->type, uregion_getType(r) );
383 log_data_err("ERROR: Known region %s was not recognized.\n", rd->code);
389 const KnownRegion * rd; local
418 const KnownRegion * rd; local
447 const KnownRegion * rd; local
471 const KnownRegion * rd; local
548 const KnownRegion * rd; local
[all...] |
| /external/chromium_org/third_party/libvpx/source/libvpx/vp9/encoder/ |
| vp9_rd.c | 47 // The baseline rd thresholds for breaking out of the rd loop for
219 static void set_block_thresholds(const VP9_COMMON *cm, RD_OPT *rd) {
236 rd->threshes[segment_id][bsize][i] =
237 rd->thresh_mult[i] < thresh_max
238 ? rd->thresh_mult[i] * t / 4
242 rd->threshes[segment_id][bsize][i] =
243 rd->thresh_mult_sub8x8[i] < thresh_max
244 ? rd->thresh_mult_sub8x8[i] * t / 4
254 RD_OPT *const rd = &cpi->rd local
525 RD_OPT *const rd = &cpi->rd; local
583 RD_OPT *const rd = &cpi->rd; local
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcJITInfo.cpp | 102 #define SETHI_INST(imm, rd) (0x01000000 | ((rd) << 25) | ((imm) & 0x3FFFFF))
103 #define JMP_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x38 << 19) \
106 #define OR_INST_I(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \
108 #define OR_INST_R(rs1, rs2, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \
110 #define RDPC_INST(rd) (0x80000000 | ((rd) << 25) | (0x28 << 19)
[all...] |
| /art/compiler/utils/arm/ |
| assembler_thumb2.h | 65 void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
67 void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
69 void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
70 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
72 void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
73 void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
75 void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
77 void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
79 void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
81 void sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE
[all...] |
| assembler_arm32.h | 43 void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
45 void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
47 void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
48 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
50 void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
51 void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
53 void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
55 void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
57 void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
59 void sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE
[all...] |
| assembler_arm32.cc | 28 void Arm32Assembler::and_(Register rd, Register rn, const ShifterOperand& so,
30 EmitType01(cond, so.type(), AND, 0, rn, rd, so);
34 void Arm32Assembler::eor(Register rd, Register rn, const ShifterOperand& so,
36 EmitType01(cond, so.type(), EOR, 0, rn, rd, so);
40 void Arm32Assembler::sub(Register rd, Register rn, const ShifterOperand& so,
42 EmitType01(cond, so.type(), SUB, 0, rn, rd, so);
45 void Arm32Assembler::rsb(Register rd, Register rn, const ShifterOperand& so,
47 EmitType01(cond, so.type(), RSB, 0, rn, rd, so);
50 void Arm32Assembler::rsbs(Register rd, Register rn, const ShifterOperand& so,
52 EmitType01(cond, so.type(), RSB, 1, rn, rd, so)
[all...] |
| assembler_arm.h | 128 static bool CanHoldThumb(Register rd, Register rn, Opcode opcode,
363 virtual void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
365 virtual void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
367 virtual void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
368 virtual void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
370 virtual void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
371 virtual void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
373 virtual void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
375 virtual void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
377 virtual void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0
[all...] |
| /external/clang/test/CXX/dcl.decl/dcl.init/dcl.init.ref/ |
| p5-examples.cpp | 6 // CHECK: VarDecl{{.*}}rd 'double &'
8 double &rd = d; local
|
| /external/chromium_org/third_party/libwebp/enc/ |
| quant.c | 54 const VP8ModeScore* const rd) {
70 (int)rd->D, (int)rd->SD, (int)rd->R, (int)rd->H, (int)rd->nz,
71 (int)rd->score);
73 printf("Mode: %d\n", rd->mode_i16);
75 for (i = 0; i < 16; ++i) printf("%3d ", rd->y_dc_levels[i]);
79 for (i = 0; i < 16; ++i) printf("%d ", rd->modes_i4[i])
[all...] |
| /external/webp/src/enc/ |
| quant.c | 54 const VP8ModeScore* const rd) {
70 (int)rd->D, (int)rd->SD, (int)rd->R, (int)rd->H, (int)rd->nz,
71 (int)rd->score);
73 printf("Mode: %d\n", rd->mode_i16);
75 for (i = 0; i < 16; ++i) printf("%3d ", rd->y_dc_levels[i]);
79 for (i = 0; i < 16; ++i) printf("%d ", rd->modes_i4[i])
[all...] |
| /external/openssl/crypto/bn/asm/ |
| sparcv8.S | 63 rd %y,%g1
74 rd %y,%g1
85 rd %y,%g1
95 rd %y,%g1
117 rd %y,%g1
128 rd %y,%g1
140 rd %y,%g1
176 rd %y,%g1
183 rd %y,%g1
191 rd %y,%g
[all...] |
