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Searched
refs:regNo
(Results
1 - 6
of
6
) sorted by null
/external/valgrind/main/VEX/priv/
host_generic_regs.c
60
Int
regNo
= hregNumber(r);
62
case HRcInt32: vex_printf("%%%sr%d", maybe_v,
regNo
); return;
63
case HRcInt64: vex_printf("%%%sR%d", maybe_v,
regNo
); return;
64
case HRcFlt32: vex_printf("%%%sF%d", maybe_v,
regNo
); return;
65
case HRcFlt64: vex_printf("%%%sD%d", maybe_v,
regNo
); return;
66
case HRcVec64: vex_printf("%%%sv%d", maybe_v,
regNo
); return;
67
case HRcVec128: vex_printf("%%%sV%d", maybe_v,
regNo
); return;
guest_arm64_toIR.c
[
all
...]
/external/llvm/lib/Target/ARM/
ARMCallingConv.h
234
for (unsigned
regNo
= 0;
regNo
< 16; ++
regNo
)
235
State.AllocateReg(SRegList[
regNo
]);
/external/llvm/lib/Target/R600/MCTargetDesc/
R600MCCodeEmitter.cpp
60
unsigned getHWReg(unsigned
regNo
) const;
166
unsigned R600MCCodeEmitter::getHWReg(unsigned
RegNo
) const {
167
return MRI.getEncodingValue(
RegNo
) & HW_REG_MASK;
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
R600MCCodeEmitter.cpp
83
unsigned getHWReg(unsigned
regNo
) const;
610
unsigned R600MCCodeEmitter::getHWReg(unsigned
RegNo
) const {
613
HWReg = getHWRegIndex(
RegNo
);
614
if (AMDGPUMCRegisterClasses[AMDGPU::R600_CReg32RegClassID].contains(
RegNo
)) {
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
R600MCCodeEmitter.cpp
83
unsigned getHWReg(unsigned
regNo
) const;
610
unsigned R600MCCodeEmitter::getHWReg(unsigned
RegNo
) const {
613
HWReg = getHWRegIndex(
RegNo
);
614
if (AMDGPUMCRegisterClasses[AMDGPU::R600_CReg32RegClassID].contains(
RegNo
)) {
Completed in 245 milliseconds