| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
494 SDLoc DL, SelectionDAG &DAG) const {
495 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
505 SelectionDAG &DAG = CLI.DAG;
507 const Function &Fn = *DAG.getMachineFunction().getFunction();
517 DAG.getContext()->diagnose(NoCalls);
522 SelectionDAG &DAG) const {
529 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
530 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
11 // selection DAG.
175 SDLoc DL, SelectionDAG &DAG) const {
177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
186 SDLoc DL, SelectionDAG &DAG) const {
187 MachineFunction &MF = DAG.getMachineFunction();
193 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
194 DAG.getTarget(), RVLocs, *DAG.getContext())
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
562 SelectionDAG &DAG) const {
569 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
576 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
583 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
590 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
597 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
602 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
625 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
631 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value
[all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| BBVectorize.cpp | 315 DenseMap<ValuePair, size_t> &DAG,
326 DenseMap<ValuePair, size_t> &DAG, ValuePair J);
776 // the pairing with the largest dag meeting the depth requirement on at
777 // least one branch. Then select all pairings that are part of that dag
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
11 // selection DAG.
85 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
86 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
87 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
91 SelectionDAG &DAG,
93 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
97 SelectionDAG &DAG,
99 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
103 SelectionDAG &DAG,
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
11 // selection DAG.
73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
77 SelectionDAG &DAG, SDLoc dl,
84 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
89 return DAG.getUNDEF(ResultVT);
101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
105 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
112 /// Generate a DAG to grab 128-bits from a vector > 128 bits. Thi
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
44 STATISTIC(NodesCombined , "Number of dag nodes combined");
54 cl::desc("Enable DAG combiner alias-analysis heuristics"));
58 cl::desc("Enable DAG combiner's use of IR alias analysis"));
62 cl::desc("Enable DAG combiner's use of TBAA"));
67 cl::desc("Only use DAG-combiner alias analysis in this"
82 SelectionDAG &DAG;
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
570 const SelectionDAG &DAG, unsigned Depth) const {
576 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
577 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
11 // selection DAG.
450 // In another words, find a way when "copysign" appears in DAG with vector
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
639 // We have target-specific dag combine patterns for the following nodes:
[all...] |
| /prebuilts/eclipse/maven/apache-maven-3.2.1/lib/ |
| plexus-utils-3.0.17.jar | |
| /prebuilts/eclipse/mavenplugins/tycho/tycho-dependencies-m2repo/org/codehaus/plexus/plexus-utils/2.0.5/ |
| plexus-utils-2.0.5.jar | |
| /prebuilts/eclipse/mavenplugins/tycho/tycho-dependencies-m2repo/org/codehaus/plexus/plexus-utils/3.0/ |
| plexus-utils-3.0.jar | |
| /prebuilts/eclipse/mavenplugins/tycho/tycho-dependencies-m2repo/org/codehaus/plexus/plexus-utils/3.0.7/ |
| plexus-utils-3.0.7.jar | |
| /prebuilts/tools/common/m2/repository/org/codehaus/plexus/plexus-utils/1.5.1/ |
| plexus-utils-1.5.1.jar | |
| /prebuilts/tools/common/m2/repository/org/codehaus/plexus/plexus-utils/3.0.7/ |
| plexus-utils-3.0.7.jar | |
| /prebuilts/tools/common/eclipse/ |
| org.eclipse.ui.workbench.texteditor_3.6.1.r361_v20100714-0800.jar | |
