/external/llvm/lib/Target/X86/MCTargetDesc/ |
X86AsmBackend.cpp | 530 unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true); 531 SavedRegs[SavedRegIdx++] = Reg; 610 int getCompactUnwindRegNum(unsigned Reg) const { 619 if (*CURegs == Reg) 633 unsigned Reg = SavedRegs[i]; 634 if (Reg == 0) break; 636 int CURegNum = getCompactUnwindRegNum(Reg);
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/external/llvm/lib/Target/X86/ |
X86MCInstLower.cpp | 249 unsigned Reg = Inst.getOperand(0).getReg(); 250 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 310 unsigned Reg = Inst.getOperand(RegOp).getReg(); 311 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreFrameLowering.cpp | 51 unsigned Reg; 52 StackSlotInfo(int f, int o, int r) : FI(f), Offset(o), Reg(r){}; 201 BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg) 286 MBB.addLiveIn(SpillList[i].Reg); 288 .addReg(SpillList[i].Reg, RegState::Kill) 293 unsigned DRegNum = MRI->getDwarfRegNum(SpillList[i].Reg, true); 329 MRI->getDwarfRegNum(SpillList[0].Reg, true), 332 MRI->getDwarfRegNum(SpillList[1].Reg, true), 426 unsigned Reg = it->getReg(); 427 assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) & [all...] |
/prebuilts/python/darwin-x86/2.7.5/lib/python2.7/distutils/ |
msvc9compiler.py | 64 class Reg: 134 self.macros["$(%s)" % macro] = Reg.get_value(path, key) 164 d = Reg.get_value(base, r"%s\%s" % (p, key)) 227 productdir = Reg.get_value(r"%s\Setup\VC" % vsbase, 236 productdir = Reg.get_value(r"%s\Setup\VC" % vsbase, 283 line = Reg.convert_mbcs(line)
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/prebuilts/python/linux-x86/2.7.5/lib/python2.7/distutils/ |
msvc9compiler.py | 64 class Reg: 134 self.macros["$(%s)" % macro] = Reg.get_value(path, key) 164 d = Reg.get_value(base, r"%s\%s" % (p, key)) 227 productdir = Reg.get_value(r"%s\Setup\VC" % vsbase, 236 productdir = Reg.get_value(r"%s\Setup\VC" % vsbase, 283 line = Reg.convert_mbcs(line)
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/external/chromium_org/third_party/mesa/src/src/mesa/program/ |
prog_optimize.c | 297 /* check dst reg */ 526 /* Walk through remaining instructions until the or src reg gets 842 GLuint Reg; /** The temporary register index */ 893 if (list->Intervals[k].Reg == inv->Reg) { 1078 inv.Reg = i; 1092 printf("Reg[%d] live [%d, %d]:", 1093 inv->Reg, inv->Start, inv->End); [all...] |
/external/llvm/include/llvm/CodeGen/ |
MachineFrameInfo.h | 38 unsigned Reg; 43 : Reg(R), FrameIdx(FI) {} 46 unsigned getReg() const { return Reg; }
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MachineOperand.h | 167 } Reg; 342 void setReg(unsigned Reg); 351 /// subregister Reg:SubReg. Take any existing SubReg index into account, 353 /// Reg must be a virtual register, SubIdx can be 0. 355 void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&); 358 /// Reg, taking any existing SubReg into account. For instance, 361 void substPhysReg(unsigned Reg, const TargetRegisterInfo&); 550 void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false, 576 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false, 595 Op.SmallContents.RegNo = Reg; [all...] |
/external/llvm/include/llvm/MC/ |
MCRegisterInfo.h | 71 bool contains(unsigned Reg) const { 72 unsigned InByte = Reg % 8; 73 unsigned Byte = Reg / 8; 110 uint32_t Name; // Printable name for the reg (for debugging) 139 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be 329 unsigned getSubReg(unsigned Reg, unsigned Idx) const; 332 /// Reg so its sub-register of index SubIdx is Reg. 333 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 439 /// MCSubRegIterator enumerates all sub-registers of Reg [all...] |
/external/llvm/lib/CodeGen/ |
EarlyIfConversion.cpp | 236 unsigned Reg = MO->getReg(); 239 if (MO->isDef() && TargetRegisterInfo::isPhysicalRegister(Reg)) 240 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) 243 if (!MO->readsReg() || !TargetRegisterInfo::isVirtualRegister(Reg)) 245 MachineInstr *DefMI = MRI->getVRegDef(Reg); 291 unsigned Reg = MO->getReg(); 292 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) 294 // I clobbers Reg, so it isn't live before I. 296 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) 298 // Unless I reads Reg [all...] |
LiveIntervalAnalysis.cpp | 150 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 151 if (hasInterval(Reg)) 152 OS << getInterval(Reg) << '\n'; 174 LiveInterval* LiveIntervals::createInterval(unsigned reg) { 175 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? 177 return new LiveInterval(reg, Weight); 194 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 195 if (MRI->reg_nodbg_empty(Reg)) 197 createAndComputeVirtRegInterval(Reg); 259 unsigned Reg = *Supers [all...] |
MachineBasicBlock.cpp | 100 /// list, we update its parent pointer and add its operands from reg use/def 115 /// list, we update its parent pointer and remove its operands from reg use/def 339 void MachineBasicBlock::removeLiveIn(unsigned Reg) { 341 std::find(LiveIns.begin(), LiveIns.end(), Reg); 346 bool MachineBasicBlock::isLiveIn(unsigned Reg) const { 347 livein_iterator I = std::find(livein_begin(), livein_end(), Reg); 739 unsigned Reg = OI->getReg(); 740 if (TargetRegisterInfo::isPhysicalRegister(Reg) || 741 LV->getVarInfo(Reg).removeKill(MI)) { 742 KilledRegs.push_back(Reg); [all...] |
PeepholeOptimizer.cpp | 170 unsigned Reg; 221 Reg = Def->getOperand(DefIdx).getReg(); 241 unsigned getReg() const { return Reg; } 610 unsigned Reg = MI->getOperand(0).getReg(); 615 TargetRegisterInfo::isVirtualRegister(Reg) && 616 MRI->hasOneNonDBGUse(Reg)) { 617 FoldAsLoadDefCandidates.insert(Reg); 631 unsigned Reg = MI->getOperand(0).getReg(); 632 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 633 ImmDefMIs.insert(std::make_pair(Reg, MI)) [all...] |
RegAllocFast.cpp | 72 MachineInstr *LastUse; // Last instr to use reg. 203 // Find the location Reg would belong... 703 unsigned Reg = MO.getReg(); 704 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 707 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) { 708 if (ThroughRegs.insert(Reg)) 709 DEBUG(dbgs() << ' ' << PrintReg(Reg)); 719 unsigned Reg = MO.getReg(); 720 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue [all...] |
RegAllocPBQP.cpp | 198 for (unsigned Reg = 1, e = tri->getNumRegs(); Reg != e; ++Reg) { 199 if (mri->def_empty(Reg)) 201 pregs.insert(Reg); 202 mri->setPhysRegUsed(Reg); 444 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 445 if (mri->reg_nodbg_empty(Reg)) 447 LiveInterval *li = &lis->getInterval(Reg); 453 vregsToAlloc.insert(li->reg); [all...] |
TailDuplication.cpp | 343 static bool isDefLiveOut(unsigned Reg, MachineBasicBlock *BB, 345 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) { 437 unsigned Reg = MO.getReg(); 438 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 441 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 444 LocalVRMap.insert(std::make_pair(Reg, NewReg)); 445 if (isDefLiveOut(Reg, TailBB, MRI) || UsedByPhi.count(Reg)) 446 AddSSAUpdateEntry(Reg, NewReg, PredBB); 448 DenseMap<unsigned, unsigned>::iterator VI = LocalVRMap.find(Reg); [all...] |
TargetInstrInfo.cpp | 608 unsigned Reg = MO.getReg(); 609 if (Reg == 0) 613 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 618 if (!MRI.isConstantPhysReg(Reg, MF)) 629 if (MO.isDef() && Reg != DefReg)
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/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGFast.cpp | 388 void ScheduleDAGFast::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, 418 SDep FromDep(SU, SDep::Data, Reg); 434 static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, 437 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); 440 if (Reg == *ImpDef) 449 static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg, 455 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 503 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 504 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 505 CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI) [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64CollectLOH.cpp | 227 /// Given a couple (MBB, reg) get the corresponding set of instruction from 234 const MachineBasicBlock &MBB, unsigned reg, 243 return result[reg]; 246 /// Given a couple (reg, MI) get the corresponding set of instructions from the 249 /// MI and reg, i.e., MI defines reg. 251 /// "sets[reg]". 252 /// \pre set[reg] is valid. 253 static SetOfMachineInstr &getUses(InstrToInstrs *sets, unsigned reg, 255 return sets[reg][&MI] [all...] |
AArch64FrameLowering.cpp | 179 unsigned Reg = Info.getReg(); 189 if (HasFP && (FramePtr == Reg || Reg == AArch64::LR)) { 194 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); 375 unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true); 377 MCCFIInstruction::createDefCfa(nullptr, Reg, 2 * StackGrowth)); 390 MCCFIInstruction::createOffset(nullptr, Reg, 2 * StackGrowth)); 406 static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs) { 408 if (Reg == CSRegs[i]) 605 static unsigned getPrologueDeath(MachineFunction &MF, unsigned Reg) { [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
AArch64InstPrinter.cpp | 112 // the range 0 to (reg.size -1). 652 unsigned Reg = MI->getOperand(OpNum++).getReg(); 653 if (Reg != AArch64::XZR) 654 O << ", " << getRegisterName(Reg); [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | 86 unsigned &Reg, unsigned &Imm, 154 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' 160 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand. 165 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' 171 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2' 184 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' 242 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12' 258 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand [all...] |
/external/llvm/lib/Target/ARM/ |
Thumb2SizeReduction.cpp | 262 unsigned Reg = MO.getReg(); 263 if (Reg == 0 || Reg == ARM::CPSR) 265 Defs.insert(Reg); 271 unsigned Reg = MO.getReg(); 272 if (Defs.count(Reg)) 344 unsigned Reg = MO.getReg(); 345 if (Reg == 0 || Reg == ARM::CPSR) 347 if (isPCOk && Reg == ARM::PC [all...] |
/external/llvm/lib/Target/Mips/Disassembler/ |
MipsDisassembler.cpp | 860 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 861 Inst.addOperand(MCOperand::CreateReg(Reg)); 871 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 872 Inst.addOperand(MCOperand::CreateReg(Reg)); [all...] |
/external/llvm/lib/Target/Mips/ |
MipsAsmPrinter.cpp | 263 unsigned Reg = CSI[i].getReg(); 264 if (Mips::GPR32RegClass.contains(Reg)) 267 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); 268 if (Mips::AFGR64RegClass.contains(Reg)) { 281 unsigned Reg = CSI[i].getReg(); 282 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); 496 unsigned Reg = MO.getReg(); 497 O << '$' << MipsInstPrinter::getRegisterName(Reg); 522 unsigned Reg = MO.getReg(); 523 O << '$' << MipsInstPrinter::getRegisterName(Reg); [all...] |