| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 271 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
381 // stackless code if all local vars are reg-allocated.
553 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
732 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
734 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
740 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
742 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
748 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
750 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
764 unsigned Reg = MRI->getDwarfRegNum(FPReg, true)
[all...] |
| PPCFastISel.cpp | 71 unsigned Reg;
80 Base.Reg = 0;
382 if (Addr.Base.Reg == 0)
383 Addr.Base.Reg = getRegForValue(Obj);
387 if (Addr.Base.Reg != 0)
388 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
390 return Addr.Base.Reg != 0;
410 Addr.Base.Reg = ResultReg;
503 // Base reg with offset in range.
507 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
[all...] |
| PPCISelDAGToDAG.cpp | 66 // Make sure we re-emit a set of the global base reg if necessary
172 /// register can be improved, but it is wrong to substitute Reg+Reg for
173 /// Reg in an asm, because the load or store opcode would have to change.
212 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
213 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
[all...] |
| PPCInstrInfo.cpp | 116 unsigned Reg = DefMO.getReg();
120 if (TRI->isVirtualRegister(Reg)) {
123 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
124 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
126 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
127 PPC::CRBITRCRegClass.contains(Reg);
760 llvm_unreachable("Impossible reg-to-reg copy");
[all...] |
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 101 RegOp Reg;
135 Op->Reg.Kind = Kind;
136 Op->Reg.Num = Num;
178 return Kind == KindReg && Reg.Kind == RegKind;
182 return Reg.Num;
311 bool parseRegister(Register &Reg);
313 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
419 bool SystemZAsmParser::parseRegister(Register &Reg) {
420 Reg.StartLoc = Parser.getTok().getLoc();
429 return Error(Reg.StartLoc, "invalid register")
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 31 // Reg should be a 32-bit GPR. Return true if it is a high register rather
33 static bool isHighReg(unsigned int Reg) {
34 if (SystemZ::GRH32BitRegClass.contains(Reg))
36 assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
106 unsigned Reg = MI->getOperand(0).getReg();
107 bool IsHigh = isHighReg(Reg);
140 unsigned Reg = MI->getOperand(0).getReg();
141 unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
417 // If Reg is a virtual register, return its definition, otherwise return null.
418 static MachineInstr *getDef(unsigned Reg,
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.h | 428 /// \brief All possible values of the reg field in the ModR/M byte.
429 enum Reg {
578 Reg vvvv;
581 Reg writemask;
602 Reg opcodeRegister;
610 Reg regBase;
616 // The reg field always encodes a register
617 Reg reg; member in struct:llvm::X86Disassembler::InternalInstruction
|
| /external/llvm/utils/TableGen/ |
| AsmWriterEmitter.cpp | 529 const CodeGenRegister &Reg = *Registers[i];
535 AsmName = Reg.TheDef->getValueAsString("AsmName");
537 AsmName = Reg.getName();
541 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices");
551 Reg.TheDef->getValueAsListOfStrings("AltNames");
553 PrintFatalError(Reg.TheDef->getLoc(),
[all...] |
| AsmMatcherEmitter.cpp | 382 static ResOperand getRegOp(Record *Reg) {
385 X.Register = Reg;
787 if (Record *Reg = AsmOperands[i].SingletonReg)
788 SingletonRegisters.insert(Reg);
[all...] |
| CodeGenRegisters.cpp | 142 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]);
143 ExplicitAliases.push_back(Reg);
144 Reg->ExplicitAliases.push_back(this);
495 // Make sure all sub-registers have been visited first, so the super-reg
586 Record *Reg = Lists[i][n];
588 Name += Reg->getName();
589 Tuple.push_back(DefInit::get(Reg));
591 unsigned(Reg->getValueAsInt("CostPerUse")));
691 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]);
692 Members.insert(Reg);
[all...] |
| DAGISelMatcher.h | 878 /// Reg - The def for the register that we're emitting. If this is null, then
880 const CodeGenRegister *Reg;
883 EmitRegisterMatcher(const CodeGenRegister *reg, MVT::SimpleValueType vt)
884 : Matcher(EmitRegister), Reg(reg), VT(vt) {}
886 const CodeGenRegister *getReg() const { return Reg; }
896 return cast<EmitRegisterMatcher>(M)->Reg == Reg &&
900 return ((unsigned)(intptr_t)Reg) << 4 | VT;
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| ExprEngine.cpp | 226 SVal Reg = loc::MemRegionVal(TR);
231 State = State->bindLoc(Reg, V);
237 Reg = StoreMgr.evalDerivedToBase(Reg, *I);
240 State = State->BindExpr(Result, LC, Reg);
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | 670 unsigned Reg;
672 Reg = MI->getOperand(0).getReg();
677 MI->getOperand(0).getIndex(), Reg);
680 if (Reg == 0) {
689 OS << AP.TM.getRegisterInfo()->getName(Reg);
[all...] |
| /external/llvm/lib/CodeGen/ |
| IfConversion.cpp | [all...] |
| RegAllocGreedy.cpp | 198 return ExtraRegInfo[VirtReg.reg].Stage;
203 ExtraRegInfo[VirtReg.reg].Stage = Stage;
210 unsigned Reg = *Begin;
211 if (ExtraRegInfo[Reg].Stage == RS_New)
212 ExtraRegInfo[Reg].Stage = NewStage;
260 void reset(InterferenceCache &Cache, unsigned Reg) {
261 PhysReg = Reg;
263 Intf.setPhysReg(Cache, Reg);
498 // The queue holds (size, reg) pairs.
500 const unsigned Reg = LI->reg
[all...] |
| RegisterCoalescer.cpp | 151 /// the source value number is defined by a copy from the destination reg
152 /// see if we can merge these two destination reg valno# into a single
479 DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI));
499 int UIdx = ValSEndInst->findRegisterUseOperandIdx(IntB.reg, true);
507 CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
597 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
614 if (NewReg != IntB.reg || !IntB.Query(AValNo->def).isKill())
622 // If some of the uses of IntA.reg is already coalesced away, return false.
624 for (MachineOperand &MO : MRI->use_nodbg_operands(IntA.reg)) {
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGISel.cpp | 470 unsigned Reg =
472 if (TargetRegisterInfo::isPhysicalRegister(Reg))
475 MachineInstr *Def = RegInfo->getVRegDef(Reg);
482 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
485 // If Reg is live-in then update debug info to track its copy in a vreg.
486 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 54 unsigned Reg;
60 Address() : Kind(RegBase), Offset(0) { Base.Reg = 0; }
65 void setReg(unsigned Reg) {
67 Base.Reg = Reg;
71 return Base.Reg;
481 // reg+offset into a register.
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | 85 unsigned Reg;
92 : Offset(o), Reg(r), isKill(k), Position(p), MBBI(i), Merged(false) {}
435 // VLDM/VSTM do not support DB mode without also updating the base reg.
504 bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback.
632 unsigned Reg = memOps[i].Reg;
633 KilledRegs.insert(Reg);
634 Killer[Reg] = i;
642 unsigned Reg = memOps[i].Reg;
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 120 /// If successful, it will return true and set the \p Reg, \p IVBump
130 bool findInductionRegister(MachineLoop *L, unsigned &Reg,
236 unsigned Reg;
246 Contents.R.Reg = v;
257 return Contents.R.Reg;
270 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
320 unsigned &Reg,
348 // latch block, and see if is a result of an addition of form "reg+imm",
349 // where the "reg" is defined by the PHI node we are looking at.
416 Reg = F->second.first
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 598 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
599 MFI->LiveOuts.push_back(Reg);
600 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
631 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
634 MRI.addLiveIn(Reg);
636 SDLoc(DAG.getEntryNode()), Reg, VT);
[all...] |
| SIISelLowering.cpp | 413 unsigned Reg = VA.getLocReg();
417 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
419 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
420 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
424 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
426 Reg = MF.addLiveIn(Reg, RC);
427 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT)
[all...] |
| SIInstrInfo.cpp | 395 unsigned Reg = MI->getOperand(1).getReg();
398 MI->getOperand(2).ChangeToRegister(Reg, false);
586 unsigned Reg = MI->getOperand(i).getReg();
587 if (TargetRegisterInfo::isVirtualRegister(Reg))
591 if (!RC->contains(Reg)) {
772 unsigned Reg = MRI.createVirtualRegister(VRC);
774 Reg).addOperand(MO);
775 MO.ChangeToRegister(Reg, false);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 98 void setBaseReg(SDValue Reg) {
100 Base_Reg = Reg;
657 // Base and index reg must be 0 in order to use %rip as base.
740 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
[all...] |
