| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.cpp | 54 RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset;
97 unsigned Reg = CSRegs[I];
98 if (SystemZ::GR64BitRegClass.contains(Reg) && MRI.isPhysRegUsed(Reg)) {
140 unsigned Reg = CSI[I].getReg();
141 if (SystemZ::GR64BitRegClass.contains(Reg)) {
142 unsigned Offset = RegSpillOffsets[Reg];
145 LowGPR = Reg;
161 unsigned Reg = SystemZ::ArgGPRs[FirstGPR];
162 unsigned Offset = RegSpillOffsets[Reg];
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 187 // pc-relativeness was handled when computing the value in the reg.
208 unsigned Reg = MO.getReg();
213 Reg = getX86SubSuperRegister(Reg, VT);
215 O << X86ATTInstPrinter::getRegisterName(Reg);
350 unsigned Reg = MO.getReg();
354 Reg = getX86SubSuperRegister(Reg, MVT::i8);
357 Reg = getX86SubSuperRegister(Reg, MVT::i8, true)
[all...] |
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 219 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
220 Inst.addOperand(MCOperand::CreateReg(Reg));
231 unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
232 Inst.addOperand(MCOperand::CreateReg(Reg));
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 235 const CodeGenRegister *Reg = getRegBank().getReg(R);
240 if (RC.contains(Reg)) {
|
| DAGISelMatcherEmitter.cpp | 455 const CodeGenRegister *Reg = Matcher->getReg();
458 if (Reg && Reg->EnumValue > 255) {
460 OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
464 if (Reg) {
465 OS << getQualifiedName(Reg->TheDef) << ",\n";
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
263 if (!MRI.isLiveOut(Reg)) {
264 MRI.addLiveOut(Reg);
266 return DAG.getCopyToReg(Chain, Op.getDebugLoc(), Reg, Op.getOperand(2));
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
|
| R600InstrInfo.cpp | 349 unsigned Reg = MI->getOperand(idx).getReg();
350 switch (Reg) {
|
| SIISelLowering.cpp | 367 unsigned Reg = dstClass->getRegister(SGPRIndex);
369 DAG.ReplaceAllUsesOfValueWith(Op, CreateLiveInRegister(DAG, dstClass, Reg,
|
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 258 bool isAllocated(unsigned Reg) const {
259 return UsedRegs[Reg/32] & (1 << (Reg&31));
310 unsigned AllocateReg(unsigned Reg) {
311 if (isAllocated(Reg)) return 0;
312 MarkAllocated(Reg);
313 return Reg;
317 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
318 if (isAllocated(Reg)) return 0;
319 MarkAllocated(Reg);
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 76 bool contains(unsigned Reg) const {
77 return MC->contains(Reg);
160 /// For all Reg in SuperRC:
161 /// this->contains(Reg:Idx)
225 // Pointer to array of lane masks, one per sub-reg index.
254 /// returns true if Reg is in the range used for stack slots.
260 static bool isStackSlot(unsigned Reg) {
261 return int(Reg) >= (1 << 30);
266 static int stackSlot2Index(unsigned Reg) {
267 assert(isStackSlot(Reg) && "Not a stack slot")
[all...] |
| /external/llvm/lib/CodeGen/ |
| LiveVariables.cpp | 131 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
133 assert(MRI->getVRegDef(reg) && "Register use before def!");
137 VarInfo& VRInfo = getVarInfo(reg);
168 if (MBB == MRI->getVRegDef(reg)->getParent()) return;
179 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
183 VarInfo &VRInfo = getVarInfo(Reg);
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
219 if (TRI->isSubRegister(Reg, DefReg))
[all...] |
| MachineCSE.cpp | 82 bool isPhysDefTriviallyDead(unsigned Reg,
95 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
122 unsigned Reg = MO.getReg();
123 if (!TargetRegisterInfo::isVirtualRegister(Reg))
125 if (!MRI->hasOneNonDBGUse(Reg))
129 MachineInstr *DefMI = MRI->getVRegDef(Reg);
148 // class given a super-reg class and subreg index.
151 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
167 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
183 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
[all...] |
| PHIElimination.cpp | 86 bool isLiveIn(unsigned Reg, MachineBasicBlock *MBB);
87 bool isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB);
232 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
558 unsigned Reg = BBI->getOperand(i).getReg();
578 if (!isLiveOutPastPHIs(Reg, PreMBB) && !SplitAllCriticalEdges)
581 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
585 // If Reg is not live-in to MBB, it means it must be live-in to some
589 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
593 bool ShouldSplit = !isLiveIn(Reg, &MBB) || SplitAllCriticalEdges;
621 bool PHIElimination::isLiveIn(unsigned Reg, MachineBasicBlock *MBB)
[all...] |
| PrologEpilogInserter.cpp | 263 unsigned Reg = CSRegs[i];
265 if (F.getRegInfo().isPhysRegUsed(Reg) || F.getMMI().callsUnwindInit()) {
266 // If the reg is modified, save it!
267 CSI.push_back(CalleeSavedInfo(Reg));
285 unsigned Reg = I->getReg();
286 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
289 if (RegInfo->hasReservedSpillSlot(F, Reg, FrameIdx)) {
298 FixedSlot->Reg != Reg)
354 unsigned Reg = CSI[i].getReg()
[all...] |
| RegisterPressure.cpp | 151 const LiveRange *RegPressureTracker::getLiveRange(unsigned Reg) const {
152 if (TargetRegisterInfo::isVirtualRegister(Reg))
153 return &LIS->getInterval(Reg);
154 return LIS->getCachedRegUnit(Reg);
294 unsigned Reg = P.LiveOutRegs[i];
295 if (TargetRegisterInfo::isVirtualRegister(Reg)
296 && !RPTracker.hasUntiedDef(Reg)) {
297 increaseSetPressure(LiveThruPressure, MRI->getPressureSets(Reg));
343 void pushRegUnits(unsigned Reg, SmallVectorImpl<unsigned> &RegUnits) {
344 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
[all...] |
| /external/llvm/lib/MC/MCAnalysis/ |
| MCModuleYAML.cpp | 67 bool matchRegister(StringRef Name, unsigned &Reg) {
71 Reg = It->getValue();
242 unsigned Reg;
243 if (!IRI->matchRegister(Scalar.substr(1), Reg))
245 Val.MCOp = MCOperand::CreateReg(Reg);
|
| /external/llvm/lib/MC/MCParser/ |
| COFFAsmParser.cpp | 581 unsigned Reg;
582 if (ParseSEHRegisterNumber(Reg))
589 getStreamer().EmitWinCFIPushReg(Reg);
594 unsigned Reg;
596 if (ParseSEHRegisterNumber(Reg))
613 getStreamer().EmitWinCFISetFrame(Reg, Off);
635 unsigned Reg;
637 if (ParseSEHRegisterNumber(Reg))
655 getStreamer().EmitWinCFISaveReg(Reg, Off);
662 unsigned Reg;
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64A57FPLoadBalancing.cpp | 491 for (auto Reg : Ord) {
492 if (!AvailableRegs[Reg])
494 if ((C == Color::Even && (Reg % 2) == 0) ||
495 (C == Color::Odd && (Reg % 2) == 1))
496 return Reg;
510 int Reg = scavengeRegister(G, C, MBB);
511 if (Reg == -1) {
515 DEBUG(dbgs() << " - Scavenged register: " << TRI->getName(Reg) << "\n");
555 Substs[MO.getReg()] = Reg;
556 MO.setReg(Reg);
[all...] |
| AArch64ConditionalCompares.cpp | 223 unsigned Reg = I.getOperand(oi).getReg();
225 assert((!HeadReg || HeadReg == Reg) && "Inconsistent PHI operands");
226 HeadReg = Reg;
229 assert((!CmpBBReg || CmpBBReg == Reg) && "Inconsistent PHI operands");
230 CmpBBReg = Reg;
247 // PHI operands are (Reg, MBB) at (oi-2, oi-1).
|
| AArch64InstrInfo.cpp | 450 // cmp reg, #0 is actually subs xzr, reg, #0.
479 // cmp reg, #foo is actually ands xzr, reg, #1<<foo.
688 unsigned Reg = MO.getReg();
689 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
690 if (!OpRegCstraints->contains(Reg))
692 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
693 !MRI->constrainRegClass(Reg, OpRegCstraints))
736 assert(succeeded && "Some operands reg class are incompatible!")
[all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 67 unsigned Reg, unsigned Lane,
114 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
137 unsigned Reg = MO.getReg();
139 if (TargetRegisterInfo::isVirtualRegister(Reg))
140 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
142 return TRC->contains(Reg);
196 unsigned Reg = MO.getReg();
197 if (!TRI->isVirtualRegister(Reg))
199 MachineOperand *Op = MI->findRegisterDefOperand(Reg);
225 II = MRI->use_instr_begin(Reg), EE = MRI->use_instr_end()
[all...] |
| ARMBaseRegisterInfo.cpp | 208 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
209 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
255 unsigned Reg = Order[I];
256 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
259 unsigned Paired = getPairedGPR(Reg, !Odd, this);
262 Hints.push_back(Reg);
267 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
270 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
274 // If 'Reg' is one of the even / odd register pair and it's now change
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 324 unsigned Reg = I->getReg();
326 // If Reg is a double precision register, emit two cfa_offsets,
328 if (Mips::AFGR64RegClass.contains(Reg)) {
330 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
332 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
347 // Reg is either in GPR32 or FGR32.
349 nullptr, MRI->getDwarfRegNum(Reg, 1), Offset));
371 unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true);
373 MCCFIInstruction::createOffset(nullptr, Reg, Offset));
463 unsigned Reg = CSI[i].getReg()
[all...] |
| MipsSEInstrInfo.cpp | 62 /// the source reg along with the FrameIndex of the loaded stack slot. If
89 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
117 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
145 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
155 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
163 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
371 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
372 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
377 /// result of adding register REG and immediate IMM.
401 unsigned Reg = RegInfo.createVirtualRegister(RC)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 305 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
308 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
312 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
316 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
345 .addReg(Reg, RegState::Kill)
370 .addReg(Reg, RegState::Kill)
404 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
409 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
415 unsigned Reg1 = Reg;
416 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC)
[all...] |
