| /frameworks/av/media/libeffects/lvm/wrapper/Bundle/ |
| EffectBundle.cpp | [all...] |
| /art/compiler/utils/arm/ |
| constants_arm.h | 152 enum Shift {
154 LSL = 0, // Logical shift left
155 LSR = 1, // Logical shift right
156 ASR = 2, // Arithmetic shift right
193 // Shift instruction register fields encodings.
260 int Bits(int shift, int count) const {
261 return (InstructionBits() >> shift) & ((1 << count) - 1);
287 Shift ShiftField() const { return static_cast<Shift>(
|
| /external/clang/lib/AST/ |
| Expr.cpp | 867 int Shift = 28;
868 while ((Char >> Shift) == 0)
869 Shift -= 4;
870 for (/**/; Shift >= 0; Shift -= 4)
871 OS << Hex[(Char >> Shift) & 15];
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGISel.cpp | [all...] |
| TargetLowering.cpp | 607 // If the shift count is an invalid immediate, don't do anything.
612 // single shift. We can do this if the bottom bits (which are shifted
696 // If the shift count is an invalid immediate, don't do anything.
701 // single shift. We can do this if the top bits (which are shifted out)
734 // If this is an arithmetic shift right and only the low-bit is set, we can
735 // always convert this into a logical shr, even if the shift amount is
736 // variable. The low bit of the shift cannot be an input sign bit unless
737 // the shift amount is >= the size of the datatype, which is undefined.
747 // If the shift count is an invalid immediate, don't do anything.
[all...] |
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | 368 /// shift amount - before type legalization these can be huge.
370 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 827 // The IV bump is a power of two. Log_2(IV bump) is the shift amount.
828 unsigned Shift = Log2_32(IVBump);
830 // Generate NormR = LSR DistR, Shift.
835 .addImm(Shift);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | [all...] |
| PPCISelDAGToDAG.cpp | 104 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
378 unsigned Shift = 32;
382 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
386 // apply shift left to mask if it comes first
387 if (isShiftMask) Mask = Mask << Shift;
388 // determine which bits are made indeterminant by shift
389 Indeterminant = ~(0xFFFFFFFFu << Shift);
391 // apply shift right to mask if it comes first
392 if (isShiftMask) Mask = Mask >> Shift;
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | [all...] |
| AMDGPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 779 // allows us to convert the shift and and into an h-register extract and
783 SDValue Shift, SDValue X,
785 if (Shift.getOpcode() != ISD::SRL ||
786 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
787 !Shift.hasOneUse())
790 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
822 // allows us to fold the shift into this addressing mode. Returns false if the
826 SDValue Shift, SDValue X,
828 if (Shift.getOpcode() != ISD::SHL ||
829 !isa<ConstantSDNode>(Shift.getOperand(1))
[all...] |
| X86ISelLowering.cpp | 243 // X86 is weird, it always uses i8 for shift amounts and setcc results.
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| ScalarReplAggregates.cpp | 370 // Dynamic accesses on integers aren't yet supported. They need us to shift
372 // know whether to use a left or right shift.
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCompares.cpp | [all...] |
| /external/valgrind/main/VEX/priv/ |
| host_arm64_defs.h | 169 UChar shift; /* 0 or 12 only */ member in struct:__anon36342::__anon36343::__anon36344
178 extern ARM64RIA* ARM64RIA_I12 ( UShort imm12, UChar shift );
612 //ZZ ARMin_NShl64, // special case 64-bit shift of Dreg by immediate
662 } Shift;
882 /* Vector shift by immediate. |amt| needs to be > 0 and <
[all...] |
| host_arm_defs.h | 142 UInt shift; /* 0, 1 2 or 3 */ member in struct:__anon36418::__anon36419::__anon36421
149 extern ARMAMode1* ARMAMode1_RRS ( HReg base, HReg index, UInt shift );
606 ARMin_NShl64, // special case 64-bit shift of Dreg by immediate
641 } Shift;
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 662 unsigned Shift = ShiftedImm.ShiftAmount;
664 if (Shift != 0 && Shift != 12)
813 template<int RegWidth, int Shift>
825 if (Value == 0 && Shift != 0)
828 return (Value & ~(0xffffULL << Shift)) == 0;
831 template<int RegWidth, int Shift>
848 return (Value & ~(0xffffULL << Shift)) == 0;
1044 // A logical vector shifter is a left shift by 0, 8, 16, or 24.
1045 unsigned Shift = getShiftExtendAmount()
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 629 // Op's first operand must be a shift right.
633 // The second operand of the shift must be an immediate.
687 // The shift masks must have the same position and size.
700 // Return if the shift amount and the first bit position of mask are not the
[all...] |
| /external/llvm/lib/Transforms/Instrumentation/ |
| MemorySanitizer.cpp | [all...] |
| /external/chromium_org/v8/src/arm64/ |
| constants-arm64.h | 142 /* Add/subtract/logical shift register */ \
332 enum Shift {
[all...] |
| /external/clang/lib/Sema/ |
| SemaExpr.cpp | [all...] |
