| /external/mesa3d/src/mesa/x86/ |
| assyntax.h | 691 #define FADD2(a, b) CHOICE(fadd ARG2(a,b), fadd ARG2(a,b), fadd ARG2(b,a))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrSSE.td | [all...] |
| X86ISelLowering.h | 707 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
709 /// expanded to fmul + fadd.
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 777 /// Given operands for an FAdd, see if we can fold the result. If not, this
784 return ConstantFoldInstOperands(Instruction::FAdd, CLHS->getType(),
792 // fadd X, -0 ==> X
796 // fadd X, 0 ==> X, when we know X is not -0
801 // fadd [nnan ninf] X, (fsub [nnan ninf] 0, X) ==> 0
[all...] |
| /external/llvm/docs/ |
| CodeGenerator.rst | [all...] |
| NVPTXUsage.rst | 52 %add = fadd float %mul, %z
458 %valC = fadd float %valA, %valB
|
| /external/qemu/target-i386/ |
| ops_sse.h | 337 #define FADD(a, b) ((a) + (b))
371 SSE_HELPER_B(helper_paddb, FADD)
372 SSE_HELPER_W(helper_paddw, FADD)
373 SSE_HELPER_L(helper_paddl, FADD)
374 SSE_HELPER_Q(helper_paddq, FADD)
[all...] |
| /external/elfutils/0.153/libcpu/defs/ |
| i386 | 199 11011000,11000{freg}:fadd {freg},%st
200 11011100,11000{freg}:fadd %st,{freg}
201 11011{D}00,{mod}000{r_m}:fadd{D} {mod}{r_m}
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAG.td | 106 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
365 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 71 case ISD::FADD: R = SoftenFloatRes_FADD(N); break;
[all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeVectorOps.cpp | 245 case ISD::FADD:
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.td | 816 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>;
820 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>;
[all...] |
| /dalvik/dx/src/com/android/dx/cf/code/ |
| BytecodeArray.java | 193 * {@code fadd} becomes {@code iadd}, but
620 case ByteOps.FADD:
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| disasm-arm64.cc | 1021 FORMAT(FADD, "fadd");
[all...] |
| macro-assembler-arm64-inl.h | 548 void MacroAssembler::Fadd(const FPRegister& fd,
552 fadd(fd, fn, fm);
[all...] |
| /external/llvm/include/llvm/IR/ |
| PatternMatch.h | 400 inline BinaryOp_match<LHS, RHS, Instruction::FAdd>
402 return BinaryOp_match<LHS, RHS, Instruction::FAdd>(L, R);
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 480 (FAddSub->getOpcode() == Instruction::FAdd ||
502 Instruction *RI = (FAddSub->getOpcode() == Instruction::FAdd)
[all...] |
| InstCombineSelect.cpp | [all...] |
| /external/llvm/test/CodeGen/X86/ |
| sse2-intrinsics-x86.ll | 639 ; fadd operation forces the execution domain.
640 %a2 = fadd <2 x double> %a1, <double 0x0, double 0x4200000000000000>
|
| /external/mockito/cglib-and-asm/src/org/mockito/asm/ |
| Frame.java | 343 // -1, //FADD, // -
[all...] |
| /external/vixl/src/a64/ |
| disasm-a64.cc | 1028 FORMAT(FADD, "fadd");
[all...] |
| macro-assembler-a64.h | 534 void Fadd(const FPRegister& fd, const FPRegister& fn, const FPRegister& fm) {
536 fadd(fd, fn, fm);
[all...] |
| /dalvik/docs/ |
| java-bytecode.html | 116 <tr class="d"><td>0x62</td><td>98</td><td>fadd</td></tr>
|
| /external/chromium_org/native_client_sdk/src/doc/reference/ |
| pnacl-bitcode-abi.rst | 328 * ``fadd``
|
