| /external/compiler-rt/lib/builtins/arm/ |
| switch16.S | 36 add r0, lr, r0, lsl #1 // compute address of element in table
37 add ip, lr, ip, lsl #1 // compute address of last element in table
41 add ip, lr, r0, lsl #1 // compute label = lr + element*2
|
| /external/libvpx/libvpx/vp8/encoder/arm/armv5te/ |
| boolhuff_armv5te.asm | 86 lsl r5, r4, r6 ; range <<= shift
117 lsl r2, r2, r6 ; lowvalue <<= offset
129 lsl r2, r2, r6 ; lowvalue <<= shift
150 mov r4, r7, lsl #7 ; ((range-1) * 128)
162 lsl r5, r4, r6 ; range <<= shift
193 lsl r2, r2, r6 ; lowvalue <<= offset
205 lsl r2, r2, r6 ; lowvalue <<= shift
232 lsl r1, r1, r4 ; r1 = v << 32 - n
241 mov r4, r7, lsl #7 ; ((range-1) * 128)
256 lsl r5, r4, r6 ; range <<= shif
[all...] |
| vp8_packtokens_mbrow_armv5.asm | 84 add r4, r4, r6, lsl #3 ; a = vp8_coef_encodings + t
101 lsl r12, r6, r4 ; r12 = v << 32 - n
132 lsl r5, r4, r6 ; range <<= shift
163 lsl r2, r2, r6 ; lowvalue <<= offset
180 lsl r2, r2, r6 ; lowvalue <<= shift
189 add r12, r7, r6, lsl #4 ; b = vp8_extra_bits + t
208 lsl r12, r7, r4
230 lsl r5, r4, r6 ; range <<= shift
261 lsl r2, r2, r6 ; lowvalue <<= offset
273 lsl r2, r2, r
[all...] |
| vp8_packtokens_partitions_armv5.asm | 113 add r4, r4, r6, lsl #3 ; a = vp8_coef_encodings + t
130 lsl r12, r6, r4 ; r12 = v << 32 - n
161 lsl r5, r4, r6 ; range <<= shift
192 lsl r2, r2, r6 ; lowvalue <<= offset
209 lsl r2, r2, r6 ; lowvalue <<= shift
218 add r12, r7, r6, lsl #4 ; b = vp8_extra_bits + t
237 lsl r12, r7, r4
259 lsl r5, r4, r6 ; range <<= shift
290 lsl r2, r2, r6 ; lowvalue <<= offset
302 lsl r2, r2, r
[all...] |
| /external/libvpx/libvpx/vp8/encoder/arm/armv6/ |
| vp8_short_fdct4x4_armv6.asm | 51 pkhbt r3, r4, r6, lsl #4 ; [o1 | o0], keep in register for PART 2
52 pkhbt r6, r5, r7, lsl #4 ; [o3 | o2]
76 pkhbt r9, r9, r6, lsl #4 ; [o5 | o4], keep in register for PART 2
77 pkhbt r6, r8, r7, lsl #4 ; [o7 | o6]
101 pkhbt r2, r2, r6, lsl #4 ; [o9 | o8], keep in register for PART 2
102 pkhbt r6, r8, r7, lsl #4 ; [o11 | o10]
122 pkhbt r0, r4, r6, lsl #4 ; [o13 | o12], keep in register for PART 2
123 pkhbt r6, r5, r7, lsl #4 ; [o15 | o14]
147 lsl r8, r2, #16 ; prepare bottom halfword for scaling
149 lsl r9, r3, #16 ; prepare bottom halfword for scalin
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| 2008-11-18-ScavengerAssert.ll | 6 %asmtmp = tail call { i32, i32, i32, i32, i32 } asm "@ Inlined umul_ppmm\0A\09mov\09$2, $5, lsr #16\0A\09mov\09$0, $6, lsr #16\0A\09bic\09$3, $5, $2, lsl #16\0A\09bic\09$4, $6, $0, lsl #16\0A\09mul\09$1, $3, $4\0A\09mul\09$4, $2, $4\0A\09mul\09$3, $0, $3\0A\09mul\09$0, $2, $0\0A\09adds\09$3, $4, $3\0A\09addcs\09$0, $0, #65536\0A\09adds\09$1, $1, $3, lsl #16\0A\09adc\09$0, $0, $3, lsr #16", "=&r,=r,=&r,=&r,=r,r,r,~{cc}"(i32 %0, i32 0) nounwind ; <{ i32, i32, i32, i32, i32 }> [#uses=1]
|
| bfx.ll | 34 ; CHECK: ldr {{lr|r[0-9]+}}, [r0, [[REG1]], lsl #2]
36 ; CHECK: ldr {{lr|r[0-9]+}}, [r0, [[REG2]], lsl #2]
38 ; CHECK: ldr {{lr|r[0-9]+}}, [r0, [[REG3]], lsl #2]
|
| lsr-scale-addr-mode.ll | 21 ; CHECK: lsl{{.*}}#2]
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| scale_sig_opt.s | 37 ADD r4, r0, r3, LSL #1 @x[i] address
45 MOV r12, r5, LSL r10
58 MOV r6, r5, LSL #16 @L_tmp = x[i] << 16
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/api/ |
| armCOMM_BitDec_s.h | 148 ORR $T2, $T2, $T1, LSL #8
149 ORR $BitBuffer, $T2, $BitBuffer, LSL #16
174 MOV $Symbol, $BitBuffer, LSL $BitCount
199 MOV $Symbol, $BitBuffer, LSL $BitCount
225 ORRCS $BitBuffer, $T1, $BitBuffer, LSL #8
250 MOVS $Symbol, $BitBuffer, LSL $BitCount
255 ORRCS $BitBuffer, $T1, $BitBuffer, LSL #8
286 MOVS $Symbol, $BitBuffer, LSL $BitCount
287 ORR $BitBuffer, $T1, $BitBuffer, LSL #8
292 ORRCS $BitBuffer, $T1, $BitBuffer, LSL #
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/api/ |
| armCOMM_BitDec_s.h | 148 ORR $T2, $T2, $T1, LSL #8
149 ORR $BitBuffer, $T2, $BitBuffer, LSL #16
174 MOV $Symbol, $BitBuffer, LSL $BitCount
199 MOV $Symbol, $BitBuffer, LSL $BitCount
225 ORRCS $BitBuffer, $T1, $BitBuffer, LSL #8
250 MOVS $Symbol, $BitBuffer, LSL $BitCount
255 ORRCS $BitBuffer, $T1, $BitBuffer, LSL #8
286 MOVS $Symbol, $BitBuffer, LSL $BitCount
287 ORR $BitBuffer, $T1, $BitBuffer, LSL #8
292 ORRCS $BitBuffer, $T1, $BitBuffer, LSL #
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| omxVCM4P10_FilterDeblockingChroma_HorEdge_I_s.S | 34 SUB r0,r0,r1,LSL #1
75 SUB r0,r0,r1,LSL #2
91 SUB r0,r0,r1,LSL #1
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/encoder/arm/armv5te/ |
| boolhuff_armv5te.asm | 86 lsl r5, r4, r6 ; range <<= shift
117 lsl r2, r2, r6 ; lowvalue <<= offset
129 lsl r2, r2, r6 ; lowvalue <<= shift
150 mov r4, r7, lsl #7 ; ((range-1) * 128)
162 lsl r5, r4, r6 ; range <<= shift
193 lsl r2, r2, r6 ; lowvalue <<= offset
205 lsl r2, r2, r6 ; lowvalue <<= shift
232 lsl r1, r1, r4 ; r1 = v << 32 - n
241 mov r4, r7, lsl #7 ; ((range-1) * 128)
256 lsl r5, r4, r6 ; range <<= shif
[all...] |
| vp8_packtokens_mbrow_armv5.asm | 84 add r4, r4, r6, lsl #3 ; a = vp8_coef_encodings + t
101 lsl r12, r6, r4 ; r12 = v << 32 - n
132 lsl r5, r4, r6 ; range <<= shift
163 lsl r2, r2, r6 ; lowvalue <<= offset
180 lsl r2, r2, r6 ; lowvalue <<= shift
189 add r12, r7, r6, lsl #4 ; b = vp8_extra_bits + t
208 lsl r12, r7, r4
230 lsl r5, r4, r6 ; range <<= shift
261 lsl r2, r2, r6 ; lowvalue <<= offset
273 lsl r2, r2, r
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/encoder/arm/armv6/ |
| vp8_short_fdct4x4_armv6.asm | 51 pkhbt r3, r4, r6, lsl #4 ; [o1 | o0], keep in register for PART 2
52 pkhbt r6, r5, r7, lsl #4 ; [o3 | o2]
76 pkhbt r9, r9, r6, lsl #4 ; [o5 | o4], keep in register for PART 2
77 pkhbt r6, r8, r7, lsl #4 ; [o7 | o6]
101 pkhbt r2, r2, r6, lsl #4 ; [o9 | o8], keep in register for PART 2
102 pkhbt r6, r8, r7, lsl #4 ; [o11 | o10]
122 pkhbt r0, r4, r6, lsl #4 ; [o13 | o12], keep in register for PART 2
123 pkhbt r6, r5, r7, lsl #4 ; [o15 | o14]
147 lsl r8, r2, #16 ; prepare bottom halfword for scaling
149 lsl r9, r3, #16 ; prepare bottom halfword for scalin
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_inter_pred_chroma_vert_w16out.s | 121 lsl r10,r6,#1 @2*wd
132 lsl r7,r3,#2 @2*dst_strd
133 sub r9,r7,r10,lsl #1 @4*dst_strd - 4wd
134 lsl r12,r2,#1 @2*src_strd
136 mov r3,r3,lsl #1
173 lsl r5,r3,#2 @2*dst_strd
175 sub r9,r5,r10,lsl #1 @4*dst_strd - 4wd
176 lsl r7,r2,#1 @2*src_strd
195 add r6,r1,r3,lsl #1 @pu1_dst + dst_strd
215 lsl r12,r3,#3 @4*dst_str
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| omxVCM4P10_TransformDequantLumaDCFromPair_s.s | 196 PKHBT trRow00,in00,in10,LSL #16 ;// [1 0] = [f4:f0]
206 PKHBT trRow20,in02,in12,LSL #16 ;// [9 8] = [6 2]
214 PKHBT trRow02,in20,in30,LSL #16 ;// [3 2] = [f12:f8]
227 PKHBT trRow22,in22,in32,LSL #16 ;// [11 10] = [14 10]
273 PKHBT trCol00,rowOp00,rowOp10,LSL #16 ;// [1 0] = [f4:f0]
283 PKHBT trCol20,rowOp02,rowOp12,LSL #16 ;// [9 8] = [6 2]
291 PKHBT trCol02,rowOp20,rowOp30,LSL #16 ;// [3 2] = [f12:f8]
304 PKHBT trCol22,rowOp22,rowOp32,LSL #16 ;// [11 10] = [14 10]
361 LSL Scale, Scale, Shift ;// Scale = Scale << Shift
372 PKHBT out00, temp1, temp2, LSL #14 ;// c0w0 = | Temp2 | Temp1
[all...] |
| /external/chromium_org/third_party/libvpx/source/libvpx/vp8/common/arm/armv6/ |
| vp8_variance8x8_armv6.asm | 27 pld [r0, r1, lsl #0]
28 pld [r2, r3, lsl #0]
42 pld [r0, r1, lsl #1]
45 pld [r2, r3, lsl #1]
|
| /external/chromium_org/third_party/libvpx/source/libvpx/vp8/encoder/arm/armv5te/ |
| vp8_packtokens_partitions_armv5.asm | 113 add r4, r4, r6, lsl #3 ; a = vp8_coef_encodings + t
130 lsl r12, r6, r4 ; r12 = v << 32 - n
161 lsl r5, r4, r6 ; range <<= shift
192 lsl r2, r2, r6 ; lowvalue <<= offset
209 lsl r2, r2, r6 ; lowvalue <<= shift
218 add r12, r7, r6, lsl #4 ; b = vp8_extra_bits + t
237 lsl r12, r7, r4
259 lsl r5, r4, r6 ; range <<= shift
290 lsl r2, r2, r6 ; lowvalue <<= offset
302 lsl r2, r2, r
[all...] |
| /external/libhevc/common/arm64/ |
| ihevc_inter_pred_chroma_vert_w16inp_w16out.s | 116 lsl x2,x2,#1 //src_strd = 2* src_strd
134 lsl x7,x2,#1 //2*src_strd
135 lsl x3,x3,#1 //2*dst_strd
136 lsl x9,x6,#2 //4*wd
137 sub x6,x3,x6,lsl #1 //2*dst_strd - 2*wd
166 add x1,x1,x6,lsl #1 //pu1_dst += 2*dst_strd - 2*wd
174 lsl x7,x2,#2 //2*src_strd
175 lsl x10,x3,#2 //2*dst_strd
177 sub x14,x10,x6,lsl #1 //2*dst_strd - 2*wd
178 sub x8,x7,x6,lsl #2 //2*src_strd - 4*w
[all...] |
| /external/libvpx/libvpx/vp8/common/arm/armv6/ |
| vp8_variance8x8_armv6.asm | 27 pld [r0, r1, lsl #0]
28 pld [r2, r3, lsl #0]
42 pld [r0, r1, lsl #1]
45 pld [r2, r3, lsl #1]
|
| /external/libvpx/libvpx/vp8/common/arm/neon/ |
| loopfiltersimplehorizontaledge_neon.asm | 26 sub r3, r0, r1, lsl #1 ; move src pointer down by 2 lines
97 add r0, r0, r1, lsl #2 ; src = y_ptr + 4 * y_stride
100 add r0, r0, r1, lsl #2 ; src = y_ptr + 8* y_stride
102 add r0, r0, r1, lsl #2 ; src = y_ptr + 12 * y_stride
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-dead-def-frame-index.ll | 16 ; CHECK: adds [[TEMP:[a-z0-9]+]], sp, #4, lsl #12
|
| /external/llvm/test/CodeGen/Hexagon/ |
| ashift-left-right.ll | 4 ; CHECK: lsl
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-logical.txt | 62 # CHECK: and w1, w2, w3, lsl #2
63 # CHECK: and x1, x2, x3, lsl #2
84 # CHECK: ands w1, w2, w3, lsl #2
85 # CHECK: ands x1, x2, x3, lsl #2
106 # CHECK: bic w1, w2, w3, lsl #3
107 # CHECK: bic x1, x2, x3, lsl #3
128 # CHECK: bics w1, w2, w3, lsl #3
129 # CHECK: bics x1, x2, x3, lsl #3
150 # CHECK: eon w1, w2, w3, lsl #4
151 # CHECK: eon x1, x2, x3, lsl #
[all...] |
