| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| Norm_Corr_neon.s | 59 ADD r5, r0, r11, LSL #1 @get the &exc[k]
169 ADD r5, r10, r5, LSL #1 @L_tmp = (L_tmp << 1) + 1
170 ADD r6, r10, r6, LSL #1 @L_tmp1 = (L_tmp1 << 1) + 1
178 MOV r5, r5, LSL r10 @L_tmp = (L_tmp << exp)
184 MOV r6, r6, LSL r5 @L_tmp = (L_tmp1 << exp)
218 MOVGT r12, r12, LSL r6 @L_tmp = L_shl(L_tmp, exp_corr + exp_norm + scale)
225 ADD r10, r5, r4, LSL #1 @ get corr_norm[t] address
239 ADD r8, r8, r5, LSL #1 @ exc[k] address
240 ADD r9, r9, r6, LSL #1 @ h[i] address
241 ADD r10, r10, r6, LSL #1 @ excf[i] addres
[all...] |
| /external/chromium_org/third_party/boringssl/src/crypto/sha/asm/ |
| sha512-armv4.pl | 99 eor $t0,$t0,$Ehi,lsl#18
101 eor $t1,$t1,$Elo,lsl#18
105 eor $t0,$t0,$Ehi,lsl#14
106 eor $t1,$t1,$Elo,lsl#14
109 eor $t0,$t0,$Elo,lsl#23
110 eor $t1,$t1,$Ehi,lsl#23 @ Sigma1(e)
152 eor $t0,$t0,$Ahi,lsl#4
153 eor $t1,$t1,$Alo,lsl#4
156 eor $t0,$t0,$Alo,lsl#30
157 eor $t1,$t1,$Ahi,lsl#3
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_inter_pred_chroma_horz_w16out.s | 130 mov r5,r10,lsl #1 @2wd
170 pld [r12, r2, lsl #1]
182 pld [r4, r2, lsl #1]
199 lsl r6,#1
200 rsb r3,r5,r3,lsl #1
202 lsl r8,#1
203 rsb r7,r5,r2,lsl #1
215 pld [r12, r2, lsl #2]
216 pld [r4, r2, lsl #2]
225 @ addeq r12,r12,r2,lsl #
[all...] |
| /external/libhevc/common/arm64/ |
| ihevc_inter_pred_chroma_horz_w16out.s | 138 lsl x5, x10, #1 //2wd
178 add x20,x12, x2 , lsl #1
193 add x20,x4, x2 , lsl #1
226 lsl x6,x6,#1
227 sub x20,x5,x3,lsl #1
230 lsl x8,x8,#1
231 sub x20,x5,x2,lsl #1
244 add x20,x12, x2 , lsl #2
246 add x20,x4, x2 , lsl #2
256 // add x20,x12,x2,lsl #
[all...] |
| ihevc_inter_pred_chroma_vert.s | 125 lsl x10,x6,#1 //2*wd
136 lsl x7,x3,#1 //2*dst_strd
138 lsl x12,x2,#1 //2*src_strd
178 lsl x5,x3,#1 //2*dst_strd
181 lsl x7,x2,#1 //2*src_strd
221 lsl x12,x3,#2 //4*dst_strd
223 lsl x12,x2,#2 //4*src_strd
277 lsl x11,x2,#2
280 sub x20,x2,x2,lsl #3
282 add x14,x2,x2,lsl #
[all...] |
| /external/openssl/crypto/sha/asm/ |
| sha512-armv4.pl | 82 eor $t0,$t0,$Ehi,lsl#18
84 eor $t1,$t1,$Elo,lsl#18
88 eor $t0,$t0,$Ehi,lsl#14
89 eor $t1,$t1,$Elo,lsl#14
92 eor $t0,$t0,$Elo,lsl#23
93 eor $t1,$t1,$Ehi,lsl#23 @ Sigma1(e)
135 eor $t0,$t0,$Ahi,lsl#4
136 eor $t1,$t1,$Alo,lsl#4
139 eor $t0,$t0,$Alo,lsl#30
140 eor $t1,$t1,$Ahi,lsl#3
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| addsub-shifted.ll | 13 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #18
19 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
25 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #5
32 ; CHECK-NOT: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #19
38 ; CHECK: neg {{w[0-9]+}}, {{w[0-9]+}}, lsl #15
44 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #18
50 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #31
56 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #5
63 ; CHECK-NOT: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #19
69 ; CHECK: neg {{x[0-9]+}}, {{x[0-9]+}}, lsl #6
[all...] |
| logical_shifted_reg.ll | 43 ; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
46 ; CHECK: bic {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
50 ; CHECK: orr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
53 ; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
57 ; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
60 ; CHECK: eon {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
133 ; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
136 ; CHECK: bic {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
140 ; CHECK: orr {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
143 ; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #6
[all...] |
| arm64-arith.ll | 51 ; CHECK: lsl w0, w0, w1
60 ; CHECK: lsl x0, x0, x1
148 ; CHECK: lsl x0, x0, #1
159 ; CHECK: neg x0, [[REG]], lsl #32
232 ; CHECK-NEXT: add w0, w0, w0, lsl #3
240 ; CHECK-NEXT: lsl x8, x0, #4
249 ; CHECK-NEXT: lsl w8, w0, #3
258 ; CHECK-NEXT: add x0, x0, x0, lsl #4
266 ; CHECK-NEXT: add w0, w0, w0, lsl #1
|
| addsub.ll | 31 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
36 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}}
65 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
70 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}}
88 ; CHECK: cmp {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
|
| /external/openssl/crypto/bn/asm/ |
| armv4-gf2m.pl | 70 mov $a4,$a1,lsl#2 @ a4=a1<<2
78 and $i0,$mask,$b,lsl#2
87 eor $lo,$lo,$t1,lsl#3 @ stall
92 eor $lo,$lo,$t0,lsl#6
97 eor $lo,$lo,$t1,lsl#9
102 eor $lo,$lo,$t0,lsl#12
107 eor $lo,$lo,$t1,lsl#15
112 eor $lo,$lo,$t0,lsl#18
117 eor $lo,$lo,$t1,lsl#21
123 eor $lo,$lo,$t0,lsl#2
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| load_store.cpp | 84 ORR(AL, 0, s.reg, s.reg, reg_imm(s0, LSL, 8));
86 ORR(AL, 0, s.reg, s.reg, reg_imm(s0, LSL, 16));
91 ORR(AL, 0, s1, s1, reg_imm(s0, LSL, 8));
93 ORR(AL, 0, s.reg, s1, reg_imm(s0, LSL, 16));
141 MOV(AL, 0, d.reg, reg_imm(s, LSL, 32-h));
217 RSB(AL, 0, d, s, reg_imm(s, LSL, dbits));
223 MOV(AL, 0, d, reg_imm(s, LSL, dbits-sbits));
237 ORR(AL, 0, d, s, reg_imm(s, LSL, sbits));
315 MOV(AL, 0, ireg, reg_imm(s.reg, LSL, 32-sh));
353 else if (shift<0) ADD(AL, 0, ireg, ireg, reg_imm(dither.reg, LSL,-shift))
[all...] |
| /bionic/libc/arch-arm/cortex-a9/bionic/ |
| memcpy_base.S | 60 movs ip, r3, lsl #31
69 movs ip, r3, lsl #29
119 movs ip, r2, lsl #29
126 2: movs ip, r2, lsl #31
164 movs r12, r3, lsl #31
202 movs r12, r2, lsl #28
209 movs r12, r2, lsl #30
|
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| armSP_FFT_CToC_FC32_Radix4_unsafe_s.S | 130 LSL grpCount,subFFTSize,#2
137 MOV pointStep,subFFTNum,LSL #1
147 LSL pointStep,pointStep,#2 @// 2*grpSize
150 MOV srcStep,pointStep,LSL #1 @// srcStep = 2*pointStep
156 MOV dstStep,outPointStep,LSL #1
171 MOV twStep,stepTwiddle,LSL #2
314 SUB pDst,pSrc,outPointStep,LSL #2
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-arm.cc | 112 COMPARE(eor(r4, r5, Operand(r6, LSL, 0)),
114 COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC),
115 "e0354087 eors r4, r5, r7, lsl #1");
116 COMPARE(eor(r4, r5, Operand(r8, LSL, 2), LeaveCC, ne),
117 "10254108 eorne r4, r5, r8, lsl #2");
118 COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs),
119 "20354189 eorcss r4, r5, r9, lsl #3");
121 COMPARE(sub(r5, r6, Operand(r10, LSL, 31), LeaveCC, hs),
122 "20465f8a subcs r5, r6, r10, lsl #31");
123 COMPARE(sub(r5, r6, Operand(r10, LSL, 30), SetCC, cc)
[all...] |
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| residu_asm_opt.s | 37 ORR r5, r6, r5, LSL #16 @r5 --- a0, a1
41 ORR r6, r7, r6, LSL #16 @r6 --- a2, a3
45 ORR r7, r8, r7, LSL #16 @r7 --- a4, a5
49 ORR r8, r9, r8, LSL #16 @r8 --- a6, a7
53 ORR r9, r10, r9, LSL #16 @r9 --- a8, a9
57 ORR r10, r11, r10, LSL #16 @r10 --- a10, a11
61 ORR r11, r12, r11, LSL #16 @r11 --- a12, a13
65 ORR r12, r4, r12, LSL #16 @r12 --- a14, a15
73 ORR r14, r4, r14, LSL #16 @r14 --- loopnum, a16
|
| /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
| sad_mb_offset.h | 84 x10 = x10 | (x11 << (32 - SHIFT)); /* bic x10, x10, x11, lsl #8 = ~G ~F ~E ~D */
162 BIC x10, x10, x11, lsl #(32-SHIFT);
164 BIC x11, x11, x12, lsl #(32-SHIFT);
185 BIC x10, x10, x11, lsl #(32-SHIFT);
187 BIC x11, x11, x12, lsl #(32-SHIFT);
256 "bic %0, %0, %1, lsl %6\n\t"
258 "bic %1, %1, %2, lsl %6\n\t"
278 "bic %0, %0, %1, lsl %6\n\t"
280 "bic %1, %1, %2, lsl %6\n\t"
|
| /bionic/libc/arch-arm64/generic/bionic/ |
| memchr.S | 80 movk wtmp2, #0x4010, lsl #16
106 lsl tmp, soff, #1
108 lsl synd, synd, tmp
143 neg tmp, tmp, lsl #1
144 lsl synd, synd, tmp
|
| /external/chromium_org/third_party/webrtc/modules/audio_coding/codecs/isac/fix/source/ |
| lattice_neon.S | 52 sub r6, r5, lsl #2
130 add r8, r8, r5, lsl #1 @ tmp32b = *ptr2 + (tmp32a << 1)
132 lsl r6, #16
140 lsl r5, r5, #1
141 add r5, r6, lsl #1
|
| /external/libhevc/decoder/arm/ |
| ihevcd_itrans_recon_dc_luma.s | 66 lsl r4,r10,r4 @ trans_size = (1 << log2_trans_size)@
70 add r8,r6,r5,lsl #6
72 add r5,r7,r8,lsl #6
142 add r0,r0,r2,lsl #3
143 add r1,r1,r3,lsl #3
|
| /external/libhevc/decoder/arm64/ |
| ihevcd_itrans_recon_dc_luma.s | 67 lsl x4,x10,x4 // trans_size = (1 << log2_trans_size)//
71 add x8,x6,x5,lsl #6
84 add x5,x7,x8,lsl #6
165 add x0,x0,x2,lsl #3
166 add x1,x1,x3,lsl #3
|
| /external/webrtc/src/modules/audio_coding/codecs/isac/fix/source/ |
| lattice_neon.S | 59 sub r6, r5, lsl #2
137 add r8, r8, r5, lsl #1 @ tmp32b = *ptr2 + (tmp32a << 1)
139 lsl r6, #16
147 lsl r5, r5, #1
148 add r5, r6, lsl #1
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| omxVCM4P10_TransformDequantChromaDCFromPair_s.s | 97 AND strOffset, cstOffset, Flag, LSL #1 ;// strOffset = (Flag & 15) < 1;
99 ORRNE Value,Value,Value2, LSL #8 ;// Value = (OMX_U16) *pSrc++
123 LSL Scale, Scale, Shift ;// Scale = Scale << Shift
131 PKHBT c0w0, Temp2, Temp1, LSL #15 ;// c0w0 = | Temp1 | Temp2 |
132 PKHBT c1w0, Temp4, Temp3, LSL #15 ;// c1w0 = | Temp3 | Temp4 |
|
| /system/core/libpixelflinger/arch-arm64/ |
| t32cb16blend.S | 76 orr w18, \FB, w16, lsl #(16 + 11)
87 orr w18, \FB, w6, lsl #(16 + 5)
98 orr w18, \FB, w16, lsl #16
112 lsl w18, w16, #11
124 orr w18, \FB, w6, lsl #5
|
| /system/core/libpixelflinger/ |
| col32cb16blend_neon.S | 125 mov r11, r11, lsl #5 // prescale red
126 mov r12, r12, lsl #6 // prescale green
127 mov r4, r4, lsl #5 // prescale blue
142 mov r6, r6, lsl #11 // shift red into 565
143 orr r6, r7, lsl #5 // shift green into 565
|
