| /external/llvm/test/CodeGen/AArch64/ |
| arm64-bitfield-extract.ll | 132 ; lsl is an alias of ubfm
133 ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], [[REG1]], #2
177 ; CHECK-NEXT: lsl [[REG2:x[0-9]+]], [[REG1]], #2
197 ; lsl is an alias of ubfm
198 ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], [[REG1]], #2
217 ; lsl is an alias of ubfm
218 ; CHECK-NEXT: lsl [[REG2:x[0-9]+]], [[REG1]], #2
295 ; lsl is an alias of ubfm
296 ; CHECK-NEXT: lsl [[REG3:w[0-9]+]], [[REG2]], #2
325 ; lsl is an alias of ubf
[all...] |
| arm64-atomic.ll | 135 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
160 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
185 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
210 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
240 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
262 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
284 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
306 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
|
| dp2.ll | 46 ; CHECK: {{lsl|lslv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
89 ; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
140 ; in the DAG (the RHS may be natively 64-bit), but we should still use the lsl instructions.
146 ; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
| /external/llvm/test/MC/AArch64/ |
| arm64-diags.s | 217 ; CHECK-ERRORS: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
222 orr w0, w0, w0, lsl #32
223 ; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
224 ; CHECK-ERRORS: orr w0, w0, w0, lsl #32
226 eor w0, w0, w0, lsl #32
227 ; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
228 ; CHECK-ERRORS: eor w0, w0, w0, lsl #32
230 and w0, w0, w0, lsl #32
231 ; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
232 ; CHECK-ERRORS: and w0, w0, w0, lsl #3
[all...] |
| inline-asm-modifiers.s | 43 add x0, x0, #:dtprel_hi12:var_tlsld, lsl #12
46 add x0, x0, #:tprel_hi12:var_tlsle, lsl #12
|
| /bionic/libc/arch-arm/krait/bionic/ |
| memset.S | 95 movs ip, r2, lsl #29
100 2: movs ip, r2, lsl #31
|
| /external/chromium_org/third_party/WebKit/Source/wtf/asm/ |
| SaturatedArithmeticARM.h | 66 "lsl %[output],%[shift]"
96 "lsl %[output],%[shift]"
|
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/arm64/ |
| armSP_FFT_CToC_FC32_Radix2_ls_s.S | 82 lsl outPointStep, subFFTSize, #3
87 LSL grpCount,subFFTSize,#1
|
| /external/chromium_org/third_party/skia/src/opts/ |
| memset16_neon.S | 32 lsl r2, r2, #1
53 orr r1, r1, r1, lsl #16
|
| /external/libhevc/common/arm/ |
| ihevc_inter_pred_luma_vert_w16inp_w16out.s | 120 mov r6,r3,lsl #1
123 mov r2, r2, lsl #1
124 sub r12,r2,r2,lsl #2 @src_ctrd & pi1_coeff
141 rsb r9,r5,r6,lsl #2 @r6->dst_strd r5 ->wd
142 rsb r8,r5,r2,lsl #2 @r2->src_strd
149 @mov r2, r2, lsl #1
175 addle r0,r0,r8,lsl #0
236 addle r0,r0,r8,lsl #0
|
| /external/llvm/test/CodeGen/ARM/ |
| prefetch.ll | 57 ; ARM: pld [r0, r1, lsl #2]
60 ; THUMB2: pld [r0, r1, lsl #2]
|
| zextload_demandedbits.ll | 11 ; CHECK: lsl
|
| /external/skia/src/opts/ |
| memset16_neon.S | 31 lsl r2, r2, #1
52 orr r1, r1, r1, lsl #16
|
| /external/tremolo/Tremolo/ |
| floor1ARM.s | 54 LDR r5,[r2],r3,LSL #2 @ r5 = *floor r2 = floor+base
60 ADC r5, r6, r5, LSL #17 @ r5 = MULT31_SHIFT15
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| pred_lt4_1_neon.s | 37 SUB r4, r0, r1, LSL #1 @ x = exc - T0
49 ADD r11, r11, r2, LSL #6 @ get inter4_2[k][]
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| omxVCM4P10_FilterDeblockingChroma_VerEdge_I_s.S | 90 SUB r0,r0,r1,LSL #3
127 SUB r0,r0,r1,LSL #3
|
| /external/chromium_org/third_party/boringssl/linux-arm/crypto/sha/ |
| sha256-armv4.S | 37 add r2,r1,r2,lsl#6 @ len to point at the end of inp
70 orr r2,r2,r12,lsl#8
72 orr r2,r2,r0,lsl#16
77 orr r2,r2,r12,lsl#24
126 orr r2,r2,r3,lsl#8
128 orr r2,r2,r0,lsl#16
133 orr r2,r2,r3,lsl#24
182 orr r2,r2,r12,lsl#8
184 orr r2,r2,r0,lsl#16
189 orr r2,r2,r12,lsl#2
[all...] |
| /external/chromium_org/third_party/libvpx/source/libvpx/vp8/common/arm/armv6/ |
| vp8_variance_halfpixvar16x16_hv_armv6.asm | 29 pld [r0, r1, lsl #0]
30 pld [r2, r3, lsl #0]
60 pld [r0, r1, lsl #1]
63 pld [r2, r3, lsl #1]
|
| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| armSP_FFT_CToC_SC32_Radix4_fs_unsafe_s.S | 125 MOV pointStep,subFFTNum,LSL #1
139 @//MOV setStep,pointStep,LSL #1
140 MOV setStep,grpSize,LSL #4
146 MOV step1,pointStep,LSL #1 @// step1 = 2*pointStep
|
| /external/libvpx/libvpx/vp8/common/arm/armv6/ |
| vp8_variance_halfpixvar16x16_hv_armv6.asm | 29 pld [r0, r1, lsl #0]
30 pld [r2, r3, lsl #0]
60 pld [r0, r1, lsl #1]
63 pld [r2, r3, lsl #1]
|
| /external/linux-tools-perf/perf-3.12.0/arch/avr32/lib/ |
| memset.S | 65 lsl r9, 1
|
| /external/llvm/test/CodeGen/Thumb/ |
| inlineasm-imm-thumb.ll | 35 %y = call i32 asm "lsl $0, $1, $2", "=r,r,N"( i32 %x, i32 31 ) nounwind
|
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-add5.ll | 12 ; CHECK: add.w r0, r0, r1, lsl #5
|
| thumb2-and.ll | 12 ; CHECK: and.w r0, r0, r1, lsl #5
|
| thumb2-cmp2.ll | 22 ; CHECK: cmp.w {{.*}}, r1, lsl #5
|
